-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo 

-- ============================================================
-- File Name: fifo_data.vhd
-- Megafunction Name(s):
-- 			dcfifo
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 4.0 Build 190 1/28/2004 SJ Full Version
-- ************************************************************


--Copyright (C) 1991-2004 Altera Corporation
--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--support information,  device programming or simulation file,  and any other
--associated  documentation or information  provided by  Altera  or a partner
--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--other  use  of such  megafunction  design,  netlist,  support  information,
--device programming or simulation file,  or any other  related documentation
--or information  is prohibited  for  any  other purpose,  including, but not
--limited to  modification,  reverse engineering,  de-compiling, or use  with
--any other  silicon devices,  unless such use is  explicitly  licensed under
--a separate agreement with  Altera  or a megafunction partner.  Title to the
--intellectual property,  including patents,  copyrights,  trademarks,  trade
--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--support  information,  device programming or simulation file,  or any other
--related documentation or information provided by  Altera  or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.


--dcfifo ADD_RAM_OUTPUT_REGISTER=ON CBX_AUTO_BLACKBOX=ON CLOCKS_ARE_SYNCHRONIZED=FALSE DEVICE_FAMILY=Cyclone LPM_NUMWORDS=256 LPM_SHOWAHEAD=OFF LPM_WIDTH=12 LPM_WIDTHU=8 OVERFLOW_CHECKING=ON UNDERFLOW_CHECKING=ON USE_EAB=ON aclr data q rdclk rdempty rdfull rdreq wrclk wrempty wrfull wrreq lpm_hint=RAM_BLOCK_TYPE=AUTO RAM_BLOCK_TYPE=AUTO
--VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_dcfifo 2004:01:14:13:39:58:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_scfifo 2003:11:25:13:14:44:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END


--a_gray2bin CBX_AUTO_BLACKBOX=ON device_family=Cyclone WIDTH=8 bin gray
--VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_dcfifo 2004:01:14:13:39:58:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_scfifo 2003:11:25:13:14:44:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END

--synthesis_resources = 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  fifo_data_a_gray2bin_ek6 IS 
	 PORT 
	 ( 
		 bin	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0);
		 gray	:	IN  STD_LOGIC_VECTOR (7 DOWNTO 0)
	 ); 
 END fifo_data_a_gray2bin_ek6;

 ARCHITECTURE RTL OF fifo_data_a_gray2bin_ek6 IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 SIGNAL  xor0 :	STD_LOGIC;
	 SIGNAL  xor1 :	STD_LOGIC;
	 SIGNAL  xor2 :	STD_LOGIC;
	 SIGNAL  xor3 :	STD_LOGIC;
	 SIGNAL  xor4 :	STD_LOGIC;
	 SIGNAL  xor5 :	STD_LOGIC;
	 SIGNAL  xor6 :	STD_LOGIC;
 BEGIN

	bin <= ( gray(7) & xor6 & xor5 & xor4 & xor3 & xor2 & xor1 & xor0);
	xor0 <= (gray(0) XOR xor1);
	xor1 <= (gray(1) XOR xor2);
	xor2 <= (gray(2) XOR xor3);
	xor3 <= (gray(3) XOR xor4);
	xor4 <= (gray(4) XOR xor5);
	xor5 <= (gray(5) XOR xor6);
	xor6 <= (gray(7) XOR gray(6));

 END RTL; --fifo_data_a_gray2bin_ek6


--dffpipe CBX_AUTO_BLACKBOX=ON DELAY=3 WIDTH=8 clock clrn d q
--VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_dcfifo 2004:01:14:13:39:58:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_scfifo 2003:11:25:13:14:44:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END


--dffpipe CBX_AUTO_BLACKBOX=ON DELAY=3 WIDTH=8 clock clrn d q
--VERSION_BEGIN 4.0 cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END

--synthesis_resources = lut 24 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  fifo_data_dffpipe_mb5 IS 
	 PORT 
	 ( 
		 clock	:	IN  STD_LOGIC;
		 clrn	:	IN  STD_LOGIC := '1';
		 d	:	IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
		 q	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0)
	 ); 
 END fifo_data_dffpipe_mb5;

 ARCHITECTURE RTL OF fifo_data_dffpipe_mb5 IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 ATTRIBUTE ALTERA_INTERNAL_OPTION : string;
	 ATTRIBUTE ALTERA_INTERNAL_OPTION OF RTL : ARCHITECTURE IS "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

	 SIGNAL	dffe31a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_dffe31a_w_lg_Q47w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL	dffe32a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_dffe32a_w_lg_Q48w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL	dffe33a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_dffpipe30_w_lg_d46w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_dffpipe30_w_lg_sclr45w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  ena	:	STD_LOGIC;
	 SIGNAL  prn	:	STD_LOGIC;
	 SIGNAL  sclr	:	STD_LOGIC;
 BEGIN

	loop0 : FOR i IN 0 TO 7 GENERATE 
		wire_dffpipe30_w_lg_d46w(i) <= d(7 DOWNTO 0)(i) AND wire_dffpipe30_w_lg_sclr45w(0);
	END GENERATE loop0;
	wire_dffpipe30_w_lg_sclr45w(0) <= NOT sclr;
	ena <= '1';
	prn <= '1';
	q <= dffe33a;
	sclr <= '0';
	PROCESS (clock, prn, clrn)
	BEGIN
		IF (prn = '0') THEN dffe31a <= (OTHERS => '1');
		ELSIF (clrn = '0') THEN dffe31a <= (OTHERS => '0');
		ELSIF (clock = '1' AND clock'event) THEN 
			IF (ena = '1') THEN dffe31a <= wire_dffpipe30_w_lg_d46w;
			END IF;
		END IF;
	END PROCESS;
	loop1 : FOR i IN 0 TO 7 GENERATE 
		wire_dffe31a_w_lg_Q47w(i) <= dffe31a(i) AND wire_dffpipe30_w_lg_sclr45w(0);
	END GENERATE loop1;
	PROCESS (clock, prn, clrn)
	BEGIN
		IF (prn = '0') THEN dffe32a <= (OTHERS => '1');
		ELSIF (clrn = '0') THEN dffe32a <= (OTHERS => '0');
		ELSIF (clock = '1' AND clock'event) THEN 
			IF (ena = '1') THEN dffe32a <= wire_dffe31a_w_lg_Q47w;
			END IF;
		END IF;
	END PROCESS;
	loop2 : FOR i IN 0 TO 7 GENERATE 
		wire_dffe32a_w_lg_Q48w(i) <= dffe32a(i) AND wire_dffpipe30_w_lg_sclr45w(0);
	END GENERATE loop2;
	PROCESS (clock, prn, clrn)
	BEGIN
		IF (prn = '0') THEN dffe33a <= (OTHERS => '1');
		ELSIF (clrn = '0') THEN dffe33a <= (OTHERS => '0');
		ELSIF (clock = '1' AND clock'event) THEN 
			IF (ena = '1') THEN dffe33a <= wire_dffe32a_w_lg_Q48w;
			END IF;
		END IF;
	END PROCESS;

 END RTL; --fifo_data_dffpipe_mb5

--synthesis_resources = lut 24 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  fifo_data_alt_synch_pipe_mb5 IS 
	 PORT 
	 ( 
		 clock	:	IN  STD_LOGIC;
		 clrn	:	IN  STD_LOGIC := '1';
		 d	:	IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
		 q	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0)
	 ); 
 END fifo_data_alt_synch_pipe_mb5;

 ARCHITECTURE RTL OF fifo_data_alt_synch_pipe_mb5 IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 ATTRIBUTE ALTERA_INTERNAL_OPTION : string;
	 ATTRIBUTE ALTERA_INTERNAL_OPTION OF RTL : ARCHITECTURE IS "X_ON_VIOLATION_OPTION=OFF";

	 SIGNAL  wire_dffpipe30_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 COMPONENT  fifo_data_dffpipe_mb5
	 PORT
	 ( 
		clock	:	IN  STD_LOGIC;
		clrn	:	IN  STD_LOGIC := '1';
		d	:	IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
		q	:	OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
	 ); 
	 END COMPONENT;
 BEGIN

	q <= wire_dffpipe30_q;
	dffpipe30 :  fifo_data_dffpipe_mb5
	  PORT MAP ( 
		clock => clock,
		clrn => clrn,
		d => d,
		q => wire_dffpipe30_q
	  );

 END RTL; --fifo_data_alt_synch_pipe_mb5


--lpm_add_sub CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_WIDTH=8 dataa datab result
--VERSION_BEGIN 4.0 cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratix 2003:12:15:10:23:28:SJ  VERSION_END


--lpm_add_sub CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_WIDTH=8 dataa datab result
--VERSION_BEGIN 4.0 cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratix 2003:12:15:10:23:28:SJ  VERSION_END


--lpm_compare CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT=YES ageb dataa datab
--VERSION_BEGIN 4.0 cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


--lpm_compare CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_WIDTH=8 aeb dataa datab
--VERSION_BEGIN 4.0 cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


--lpm_compare CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT=YES ageb dataa datab
--VERSION_BEGIN 4.0 cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


--lpm_compare CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT=YES aeb dataa datab
--VERSION_BEGIN 4.0 cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


--scfifo CBX_AUTO_BLACKBOX=ON DEVICE_FAMILY=Cyclone LPM_NUMWORDS=3 LPM_SHOWAHEAD=OFF lpm_width=12 OVERFLOW_CHECKING=ON UNDERFLOW_CHECKING=ON USE_EAB=OFF aclr clock data empty full q rdreq wrreq
--VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_scfifo 2003:11:25:13:14:44:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END

 LIBRARY altera_mf;
 USE altera_mf.altera_mf_components.all;

 LIBRARY ieee;
 USE ieee.std_logic_unsigned.all;

 LIBRARY lpm;
 USE lpm.lpm_components.all;

--synthesis_resources = a_graycounter 3 altsyncram 1 lpm_counter 2 lut 134 scfifo 1 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  fifo_data_dcfifo_9d01 IS 
	 PORT 
	 ( 
		 aclr	:	IN  STD_LOGIC := '0';
		 data	:	IN  STD_LOGIC_VECTOR (11 DOWNTO 0);
		 q	:	OUT  STD_LOGIC_VECTOR (11 DOWNTO 0);
		 rdclk	:	IN  STD_LOGIC;
		 rdempty	:	OUT  STD_LOGIC;
		 rdfull	:	OUT  STD_LOGIC;
		 rdreq	:	IN  STD_LOGIC;
		 rdusedw	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0);
		 wrclk	:	IN  STD_LOGIC;
		 wrempty	:	OUT  STD_LOGIC;
		 wrfull	:	OUT  STD_LOGIC;
		 wrreq	:	IN  STD_LOGIC;
		 wrusedw	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0)
	 ); 
 END fifo_data_dcfifo_9d01;

 ARCHITECTURE RTL OF fifo_data_dcfifo_9d01 IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 ATTRIBUTE ALTERA_INTERNAL_OPTION : string;
	 ATTRIBUTE ALTERA_INTERNAL_OPTION OF RTL : ARCHITECTURE IS "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

	 SIGNAL  wire_a_gray2bin11_bin	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_a_gray2bin3_bin	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_a_graycounter2_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_a_graycounter8_clk_en	:	STD_LOGIC;
	 SIGNAL  wire_w_lg_w_lg_stall_pipeline13w14w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_a_graycounter8_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_a_graycounter9_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_altsyncram1_clocken1	:	STD_LOGIC;
	 SIGNAL  wire_altsyncram1_q_b	:	STD_LOGIC_VECTOR (11 DOWNTO 0);
	 SIGNAL	dffe16a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe18a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe19a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe20a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe21	:	STD_LOGIC
	 -- synopsys translate_off
	  := '0'
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_dffe21_w_lg_Q4w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL	dffe22	:	STD_LOGIC
	 -- synopsys translate_off
	  := '0'
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_dffe22_w_lg_Q9w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL	dffe23	:	STD_LOGIC
	 -- synopsys translate_off
	  := '0'
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe25a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe26a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe27a	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe28	:	STD_LOGIC
	 -- synopsys translate_off
	  := '0'
	 -- synopsys translate_on
	 ;
	 SIGNAL	dffe29a0	:	STD_LOGIC
	 -- synopsys translate_off
	  := '0'
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_dffe29a_w_lg_Q18w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL	dffe29a1	:	STD_LOGIC
	 -- synopsys translate_off
	  := '0'
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_alt_synch_pipe17_clrn	:	STD_LOGIC;
	 SIGNAL  wire_alt_synch_pipe17_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_alt_synch_pipe24_clrn	:	STD_LOGIC;
	 SIGNAL  wire_alt_synch_pipe24_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_add_sub12_dataa	:		STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_add_sub12_datab	:		STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_add_sub12_result	:		STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_add_sub5_dataa	:		STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_add_sub5_datab	:		STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_add_sub5_result	:		STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_cmpr13_aeb_int	:	STD_LOGIC;
	 SIGNAL  wire_cmpr13_agb_int	:	STD_LOGIC;
	 SIGNAL  wire_cmpr13_ageb	:	STD_LOGIC;
	 SIGNAL  wire_cmpr13_dataa	:	STD_LOGIC_VECTOR(7 DOWNTO 0)	;
	 SIGNAL  wire_cmpr13_datab	:	STD_LOGIC_VECTOR(7 DOWNTO 0)	;
	 SIGNAL  wire_cmpr15_aeb_int	:	STD_LOGIC;
	 SIGNAL  wire_cmpr15_aeb	:	STD_LOGIC;
	 SIGNAL  wire_cmpr15_dataa	:	STD_LOGIC_VECTOR(7 DOWNTO 0)	;
	 SIGNAL  wire_cmpr15_datab	:	STD_LOGIC_VECTOR(7 DOWNTO 0)	;
	 SIGNAL  wire_cmpr15_w_lg_aeb12w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_cmpr6_aeb_int	:	STD_LOGIC;
	 SIGNAL  wire_cmpr6_agb_int	:	STD_LOGIC;
	 SIGNAL  wire_cmpr6_ageb	:	STD_LOGIC;
	 SIGNAL  wire_cmpr6_dataa	:	STD_LOGIC_VECTOR(7 DOWNTO 0)	;
	 SIGNAL  wire_cmpr6_datab	:	STD_LOGIC_VECTOR(7 DOWNTO 0)	;
	 SIGNAL  wire_cmpr7_aeb_int	:	STD_LOGIC;
	 SIGNAL  wire_cmpr7_aeb	:	STD_LOGIC;
	 SIGNAL  wire_cmpr7_dataa	:	STD_LOGIC_VECTOR(7 DOWNTO 0)	;
	 SIGNAL  wire_cmpr7_datab	:	STD_LOGIC_VECTOR(7 DOWNTO 0)	;
	 SIGNAL  wire_cntr10_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_cntr4_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_scfifo14_empty	:	STD_LOGIC;
	 SIGNAL  wire_scfifo14_full	:	STD_LOGIC;
	 SIGNAL  wire_scfifo14_q	:	STD_LOGIC_VECTOR (11 DOWNTO 0);
	 SIGNAL  wire_w_lg_aclr3w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_w_lg_pre_rdempty10w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_w_lg_pre_wrfull1w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_w_lg_stall_pipeline13w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_w_lg_wrreq5w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  delayed_read_counter_after_gray_conversion :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  delayed_write_counter_after_gray_conversion :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  fifo_wreq_out :	STD_LOGIC;
	 SIGNAL  pre_rdempty :	STD_LOGIC;
	 SIGNAL  pre_wrfull :	STD_LOGIC;
	 SIGNAL  ramread_address :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  rdusedw_delaypipe_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  read_count_after_gray_conversion :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  read_count_for_write_side :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  read_count_to_write_side :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  stall_pipeline :	STD_LOGIC;
	 SIGNAL  valid_rreq :	STD_LOGIC;
	 SIGNAL  valid_wrreq :	STD_LOGIC;
	 SIGNAL  write_count_after_gray_conversion :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  write_count_for_read_side :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  write_count_to_read_side :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wrusedw_delaypipe_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 COMPONENT  fifo_data_a_gray2bin_ek6
	 PORT
	 ( 
		bin	:	OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
		gray	:	IN  STD_LOGIC_VECTOR(7 DOWNTO 0)
	 ); 
	 END COMPONENT;
	 COMPONENT  a_graycounter
	 GENERIC 
	 (
		PVALUE	:	NATURAL := 0;
		WIDTH	:	NATURAL;
		lpm_type	:	STRING := "a_graycounter"
	 );
	 PORT
	 ( 
		aclr	:	IN STD_LOGIC := '0';
		clk_en	:	IN STD_LOGIC := '1';
		clock	:	IN STD_LOGIC;
		cnt_en	:	IN STD_LOGIC := '1';
		q	:	OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0);
		qbin	:	OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0);
		sclr	:	IN STD_LOGIC := '0';
		updown	:	IN STD_LOGIC := '1'
	 ); 
	 END COMPONENT;
	 COMPONENT  altsyncram
	 GENERIC 
	 (
		ADDRESS_ACLR_A	:	STRING := "UNUSED";
		ADDRESS_ACLR_B	:	STRING := "NONE";
		ADDRESS_REG_B	:	STRING := "CLOCK1";
		BYTE_SIZE	:	NATURAL := 8;
		BYTEENA_ACLR_A	:	STRING := "UNUSED";
		BYTEENA_ACLR_B	:	STRING := "NONE";
		BYTEENA_REG_B	:	STRING := "CLOCK1";
		CLOCK_ENABLE_INPUT_A	:	STRING := "NORMAL";
		CLOCK_ENABLE_INPUT_B	:	STRING := "NORMAL";
		CLOCK_ENABLE_OUTPUT_A	:	STRING := "NORMAL";
		CLOCK_ENABLE_OUTPUT_B	:	STRING := "NORMAL";
		INDATA_ACLR_A	:	STRING := "UNUSED";
		INDATA_ACLR_B	:	STRING := "NONE";
		INDATA_REG_B	:	STRING := "CLOCK1";
		INIT_FILE	:	STRING := "UNUSED";
		INIT_FILE_LAYOUT	:	STRING := "PORT_A";
		MAXIMUM_DEPTH	:	NATURAL := 0;
		NUMWORDS_A	:	NATURAL := 0;
		NUMWORDS_B	:	NATURAL := 0;
		OPERATION_MODE	:	STRING := "BIDIR_DUAL_PORT";
		OUTDATA_ACLR_A	:	STRING := "NONE";
		OUTDATA_ACLR_B	:	STRING := "NONE";
		OUTDATA_REG_A	:	STRING := "UNREGISTERED";
		OUTDATA_REG_B	:	STRING := "UNREGISTERED";
		RAM_BLOCK_TYPE	:	STRING := "AUTO";
		RDCONTROL_ACLR_B	:	STRING := "NONE";
		RDCONTROL_REG_B	:	STRING := "CLOCK1";
		READ_DURING_WRITE_MODE_MIXED_PORTS	:	STRING := "DONT_CARE";
		WIDTH_A	:	NATURAL;
		WIDTH_B	:	NATURAL := 1;
		WIDTH_BYTEENA_A	:	NATURAL := 1;
		WIDTH_BYTEENA_B	:	NATURAL := 1;
		WIDTHAD_A	:	NATURAL;
		WIDTHAD_B	:	NATURAL := 1;
		WRCONTROL_ACLR_A	:	STRING := "UNUSED";
		WRCONTROL_ACLR_B	:	STRING := "NONE";
		WRCONTROL_WRADDRESS_REG_B	:	STRING := "CLOCK1";
		INTENDED_DEVICE_FAMILY	:	STRING := "Cyclone";
		lpm_type	:	STRING := "altsyncram"
	 );
	 PORT
	 ( 
		aclr0	:	IN STD_LOGIC := '0';
		aclr1	:	IN STD_LOGIC := '0';
		address_a	:	IN STD_LOGIC_VECTOR(WIDTHAD_A-1 DOWNTO 0);
		address_b	:	IN STD_LOGIC_VECTOR(WIDTHAD_B-1 DOWNTO 0) := (OTHERS => '1');
		addressstall_a	:	IN STD_LOGIC := 'Z';
		addressstall_b	:	IN STD_LOGIC := 'Z';
		byteena_a	:	IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_A-1 DOWNTO 0) := (OTHERS => 'Z');
		byteena_b	:	IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_B-1 DOWNTO 0) := (OTHERS => 'Z');
		clock0	:	IN STD_LOGIC := '1';
		clock1	:	IN STD_LOGIC := '1';
		clocken0	:	IN STD_LOGIC := '1';
		clocken1	:	IN STD_LOGIC := '1';
		data_a	:	IN STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0) := (OTHERS => '1');
		data_b	:	IN STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0) := (OTHERS => '1');
		q_a	:	OUT STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0);
		q_b	:	OUT STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0);
		rden_b	:	IN STD_LOGIC := '1';
		wren_a	:	IN STD_LOGIC := '0';
		wren_b	:	IN STD_LOGIC := '0'
	 ); 
	 END COMPONENT;
	 COMPONENT  fifo_data_alt_synch_pipe_mb5
	 PORT
	 ( 
		clock	:	IN  STD_LOGIC;
		clrn	:	IN  STD_LOGIC := '1';
		d	:	IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
		q	:	OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
	 ); 
	 END COMPONENT;
	 COMPONENT  lpm_counter
	 GENERIC 
	 (
		lpm_avalue	:	STRING := "0";
		lpm_direction	:	STRING := "UNUSED";
		lpm_modulus	:	NATURAL := 0;
		lpm_svalue	:	STRING := "0";
		lpm_width	:	NATURAL;
		lpm_type	:	STRING := "lpm_counter"
	 );
	 PORT
	 ( 
		aclr	:	IN STD_LOGIC := '0';
		aload	:	IN STD_LOGIC := '0';
		aset	:	IN STD_LOGIC := '0';
		cin	:	IN STD_LOGIC := '1';
		clk_en	:	IN STD_LOGIC := '1';
		clock	:	IN STD_LOGIC;
		cnt_en	:	IN STD_LOGIC := '1';
		cout	:	OUT STD_LOGIC;
		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
		eq	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
		q	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
		sclr	:	IN STD_LOGIC := '0';
		sload	:	IN STD_LOGIC := '0';
		sset	:	IN STD_LOGIC := '0';
		updown	:	IN STD_LOGIC := 'Z'
	 ); 
	 END COMPONENT;
	 COMPONENT  scfifo
	 GENERIC 
	 (
		ALLOW_RWCYCLE_WHEN_FULL	:	STRING := "OFF";
		ALMOST_EMPTY_VALUE	:	NATURAL := 0;
		ALMOST_FULL_VALUE	:	NATURAL := 0;
		LPM_NUMWORDS	:	NATURAL;
		LPM_SHOWAHEAD	:	STRING := "OFF";
		lpm_width	:	NATURAL;
		MAXIMIZE_SPEED	:	NATURAL := 5;
		OPTIMIZE_FOR_SPEED	:	NATURAL := 5;
		OVERFLOW_CHECKING	:	STRING := "ON";
		UNDERFLOW_CHECKING	:	STRING := "ON";
		USE_EAB	:	STRING := "ON";
		lpm_type	:	STRING := "scfifo"
	 );
	 PORT
	 ( 
		aclr	:	IN STD_LOGIC := '0';
		almost_empty	:	OUT STD_LOGIC;
		almost_full	:	OUT STD_LOGIC;
		clock	:	IN STD_LOGIC;
		data	:	IN STD_LOGIC_VECTOR(lpm_width-1 DOWNTO 0);
		empty	:	OUT STD_LOGIC;
		full	:	OUT STD_LOGIC;
		q	:	OUT STD_LOGIC_VECTOR(lpm_width-1 DOWNTO 0);
		rdreq	:	IN STD_LOGIC;
		sclr	:	IN STD_LOGIC := '0';
		usedw	:	OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
		wrreq	:	IN STD_LOGIC
	 ); 
	 END COMPONENT;
 BEGIN

	wire_w_lg_aclr3w(0) <= NOT aclr;
	wire_w_lg_pre_rdempty10w(0) <= NOT pre_rdempty;
	wire_w_lg_pre_wrfull1w(0) <= NOT pre_wrfull;
	wire_w_lg_stall_pipeline13w(0) <= NOT stall_pipeline;
	wire_w_lg_wrreq5w(0) <= NOT wrreq;
	delayed_read_counter_after_gray_conversion <= dffe18a;
	delayed_write_counter_after_gray_conversion <= dffe25a;
	fifo_wreq_out <= dffe29a1;
	pre_rdempty <= wire_scfifo14_empty;
	pre_wrfull <= dffe23;
	q <= wire_scfifo14_q;
	ramread_address <= wire_a_graycounter8_q;
	rdempty <= pre_rdempty;
	rdfull <= dffe28;
	rdusedw <= dffe27a;
	rdusedw_delaypipe_out <= dffe26a;
	read_count_after_gray_conversion <= wire_a_gray2bin3_bin;
	read_count_for_write_side <= wire_alt_synch_pipe17_q;
	read_count_to_write_side <= wire_a_graycounter9_q;
	stall_pipeline <= (wire_scfifo14_full AND dffe29a1);
	valid_rreq <= (rdreq AND wire_w_lg_pre_rdempty10w(0));
	valid_wrreq <= (wire_w_lg_pre_wrfull1w(0) AND wrreq);
	wrempty <= wire_dffe22_w_lg_Q9w(0);
	wrfull <= pre_wrfull;
	write_count_after_gray_conversion <= wire_a_gray2bin11_bin;
	write_count_for_read_side <= wire_alt_synch_pipe24_q;
	write_count_to_read_side <= dffe16a;
	wrusedw <= dffe20a;
	wrusedw_delaypipe_out <= dffe19a;
	a_gray2bin11 :  fifo_data_a_gray2bin_ek6
	  PORT MAP ( 
		bin => wire_a_gray2bin11_bin,
		gray => write_count_for_read_side
	  );
	a_gray2bin3 :  fifo_data_a_gray2bin_ek6
	  PORT MAP ( 
		bin => wire_a_gray2bin3_bin,
		gray => read_count_for_write_side
	  );
	a_graycounter2 :  a_graycounter
	  GENERIC MAP (
		WIDTH => 8
	  )
	  PORT MAP ( 
		aclr => aclr,
		clk_en => valid_wrreq,
		clock => wrclk,
		q => wire_a_graycounter2_q
	  );
	wire_a_graycounter8_clk_en <= wire_w_lg_w_lg_stall_pipeline13w14w(0);
	wire_w_lg_w_lg_stall_pipeline13w14w(0) <= wire_w_lg_stall_pipeline13w(0) AND wire_cmpr15_w_lg_aeb12w(0);
	a_graycounter8 :  a_graycounter
	  GENERIC MAP (
		WIDTH => 8
	  )
	  PORT MAP ( 
		aclr => aclr,
		clk_en => wire_a_graycounter8_clk_en,
		clock => rdclk,
		q => wire_a_graycounter8_q
	  );
	a_graycounter9 :  a_graycounter
	  GENERIC MAP (
		WIDTH => 8
	  )
	  PORT MAP ( 
		aclr => aclr,
		clk_en => valid_rreq,
		clock => rdclk,
		q => wire_a_graycounter9_q
	  );
	wire_altsyncram1_clocken1 <= wire_w_lg_stall_pipeline13w(0);
	altsyncram1 :  altsyncram
	  GENERIC MAP (
		ADDRESS_ACLR_A => "NONE",
		ADDRESS_ACLR_B => "NONE",
		ADDRESS_REG_B => "CLOCK1",
		INDATA_ACLR_A => "NONE",
		OPERATION_MODE => "DUAL_PORT",
		OUTDATA_ACLR_B => "NONE",
		OUTDATA_REG_B => "CLOCK1",
		RAM_BLOCK_TYPE => "AUTO",
		WIDTH_A => 12,
		WIDTH_B => 12,
		WIDTH_BYTEENA_A => 1,
		WIDTHAD_A => 8,
		WIDTHAD_B => 8,
		WRCONTROL_ACLR_A => "NONE",
		INTENDED_DEVICE_FAMILY => "Cyclone"
	  )
	  PORT MAP ( 
		address_a => wire_a_graycounter2_q,
		address_b => ramread_address,
		clock0 => wrclk,
		clock1 => rdclk,
		clocken1 => wire_altsyncram1_clocken1,
		data_a => data,
		q_b => wire_altsyncram1_q_b,
		wren_a => valid_wrreq
	  );
	PROCESS (wrclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe16a <= (OTHERS => '0');
		ELSIF (wrclk = '1' AND wrclk'event) THEN dffe16a <= wire_a_graycounter2_q;
		END IF;
	END PROCESS;
	PROCESS (wrclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe18a <= (OTHERS => '0');
		ELSIF (wrclk = '1' AND wrclk'event) THEN dffe18a <= read_count_after_gray_conversion;
		END IF;
	END PROCESS;
	PROCESS (wrclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe19a <= (OTHERS => '0');
		ELSIF (wrclk = '1' AND wrclk'event) THEN dffe19a <= wire_add_sub5_result;
		END IF;
	END PROCESS;
	PROCESS (wrclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe20a <= (OTHERS => '0');
		ELSIF (wrclk = '1' AND wrclk'event) THEN dffe20a <= wire_add_sub5_result;
		END IF;
	END PROCESS;
	PROCESS (wrclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe21 <= '0';
		ELSIF (wrclk = '1' AND wrclk'event) THEN dffe21 <= wrreq;
		END IF;
	END PROCESS;
	wire_dffe21_w_lg_Q4w(0) <= NOT dffe21;
	PROCESS (wrclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe22 <= '0';
		ELSIF (wrclk = '1' AND wrclk'event) THEN dffe22 <= (NOT ((wire_w_lg_wrreq5w(0) AND wire_dffe21_w_lg_Q4w(0)) AND wire_cmpr7_aeb));
		END IF;
	END PROCESS;
	wire_dffe22_w_lg_Q9w(0) <= NOT dffe22;
	PROCESS (wrclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe23 <= '0';
		ELSIF (wrclk = '1' AND wrclk'event) THEN dffe23 <= wire_cmpr6_ageb;
		END IF;
	END PROCESS;
	PROCESS (rdclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe25a <= (OTHERS => '0');
		ELSIF (rdclk = '1' AND rdclk'event) THEN dffe25a <= write_count_after_gray_conversion;
		END IF;
	END PROCESS;
	PROCESS (rdclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe26a <= (OTHERS => '0');
		ELSIF (rdclk = '1' AND rdclk'event) THEN dffe26a <= wire_add_sub12_result;
		END IF;
	END PROCESS;
	PROCESS (rdclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe27a <= (OTHERS => '0');
		ELSIF (rdclk = '1' AND rdclk'event) THEN dffe27a <= wire_add_sub12_result;
		END IF;
	END PROCESS;
	PROCESS (rdclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe28 <= '0';
		ELSIF (rdclk = '1' AND rdclk'event) THEN dffe28 <= wire_cmpr13_ageb;
		END IF;
	END PROCESS;
	PROCESS (rdclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe29a0 <= '0';
		ELSIF (rdclk = '1' AND rdclk'event) THEN dffe29a0 <= ((stall_pipeline AND dffe29a0) OR (wire_w_lg_stall_pipeline13w(0) AND wire_cmpr15_w_lg_aeb12w(0)));
		END IF;
	END PROCESS;
	wire_dffe29a_w_lg_Q18w(0) <= dffe29a0 AND wire_w_lg_stall_pipeline13w(0);
	PROCESS (rdclk, aclr)
	BEGIN
		IF (aclr = '1') THEN dffe29a1 <= '0';
		ELSIF (rdclk = '1' AND rdclk'event) THEN dffe29a1 <= (wire_dffe29a_w_lg_Q18w(0) OR (dffe29a1 AND stall_pipeline));
		END IF;
	END PROCESS;
	wire_alt_synch_pipe17_clrn <= wire_w_lg_aclr3w(0);
	alt_synch_pipe17 :  fifo_data_alt_synch_pipe_mb5
	  PORT MAP ( 
		clock => wrclk,
		clrn => wire_alt_synch_pipe17_clrn,
		d => read_count_to_write_side,
		q => wire_alt_synch_pipe17_q
	  );
	wire_alt_synch_pipe24_clrn <= wire_w_lg_aclr3w(0);
	alt_synch_pipe24 :  fifo_data_alt_synch_pipe_mb5
	  PORT MAP ( 
		clock => rdclk,
		clrn => wire_alt_synch_pipe24_clrn,
		d => write_count_to_read_side,
		q => wire_alt_synch_pipe24_q
	  );
	wire_add_sub12_result <= wire_add_sub12_dataa - wire_add_sub12_datab;
	wire_add_sub12_dataa <= delayed_write_counter_after_gray_conversion;
	wire_add_sub12_datab <= wire_cntr10_q;
	wire_add_sub5_result <= wire_add_sub5_dataa - wire_add_sub5_datab;
	wire_add_sub5_dataa <= wire_cntr4_q;
	wire_add_sub5_datab <= delayed_read_counter_after_gray_conversion;
	PROCESS (wire_cmpr13_dataa, wire_cmpr13_datab)
	BEGIN
		IF (wire_cmpr13_dataa = wire_cmpr13_datab) THEN
			wire_cmpr13_aeb_int <= '1';
			wire_cmpr13_agb_int <= '0';
		ELSIF (wire_cmpr13_dataa > wire_cmpr13_datab) THEN
			wire_cmpr13_agb_int <= '1';
			wire_cmpr13_aeb_int <= '0';
		ELSE
			wire_cmpr13_aeb_int <= '0';
			wire_cmpr13_agb_int <= '0';
		END IF;
	END PROCESS;
	wire_cmpr13_ageb <= wire_cmpr13_agb_int OR wire_cmpr13_aeb_int;
	wire_cmpr13_dataa <= rdusedw_delaypipe_out;
	wire_cmpr13_datab <= "11111101";
	PROCESS (wire_cmpr15_dataa, wire_cmpr15_datab)
	BEGIN
		IF (wire_cmpr15_dataa = wire_cmpr15_datab) THEN
			wire_cmpr15_aeb_int <= '1';
		ELSE
			wire_cmpr15_aeb_int <= '0';
		END IF;
	END PROCESS;
	wire_cmpr15_aeb <= wire_cmpr15_aeb_int;
	wire_cmpr15_dataa <= wire_a_graycounter8_q;
	wire_cmpr15_datab <= write_count_for_read_side;
	wire_cmpr15_w_lg_aeb12w(0) <= NOT wire_cmpr15_aeb;
	PROCESS (wire_cmpr6_dataa, wire_cmpr6_datab)
	BEGIN
		IF (wire_cmpr6_dataa = wire_cmpr6_datab) THEN
			wire_cmpr6_aeb_int <= '1';
			wire_cmpr6_agb_int <= '0';
		ELSIF (wire_cmpr6_dataa > wire_cmpr6_datab) THEN
			wire_cmpr6_agb_int <= '1';
			wire_cmpr6_aeb_int <= '0';
		ELSE
			wire_cmpr6_aeb_int <= '0';
			wire_cmpr6_agb_int <= '0';
		END IF;
	END PROCESS;
	wire_cmpr6_ageb <= wire_cmpr6_agb_int OR wire_cmpr6_aeb_int;
	wire_cmpr6_dataa <= wrusedw_delaypipe_out;
	wire_cmpr6_datab <= "11111101";
	PROCESS (wire_cmpr7_dataa, wire_cmpr7_datab)
	BEGIN
		IF (wire_cmpr7_dataa = wire_cmpr7_datab) THEN
			wire_cmpr7_aeb_int <= '1';
		ELSE
			wire_cmpr7_aeb_int <= '0';
		END IF;
	END PROCESS;
	wire_cmpr7_aeb <= wire_cmpr7_aeb_int;
	wire_cmpr7_dataa <= wrusedw_delaypipe_out;
	wire_cmpr7_datab <= "00000000";
	cntr10 :  lpm_counter
	  GENERIC MAP (
		lpm_direction => "UP",
		lpm_width => 8
	  )
	  PORT MAP ( 
		aclr => aclr,
		clk_en => valid_rreq,
		clock => rdclk,
		q => wire_cntr10_q
	  );
	cntr4 :  lpm_counter
	  GENERIC MAP (
		lpm_direction => "UP",
		lpm_width => 8
	  )
	  PORT MAP ( 
		aclr => aclr,
		clk_en => valid_wrreq,
		clock => wrclk,
		q => wire_cntr4_q
	  );
	scfifo14 :  scfifo
	  GENERIC MAP (
		LPM_NUMWORDS => 3,
		LPM_SHOWAHEAD => "OFF",
		lpm_width => 12,
		OVERFLOW_CHECKING => "ON",
		UNDERFLOW_CHECKING => "ON",
		USE_EAB => "OFF"
	  )
	  PORT MAP ( 
		aclr => aclr,
		clock => rdclk,
		data => wire_altsyncram1_q_b,
		empty => wire_scfifo14_empty,
		full => wire_scfifo14_full,
		q => wire_scfifo14_q,
		rdreq => rdreq,
		wrreq => fifo_wreq_out
	  );

 END RTL; --fifo_data_dcfifo_9d01
--VALID FILE


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fifo_data IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		wrreq		: IN STD_LOGIC ;
		rdreq		: IN STD_LOGIC ;
		rdclk		: IN STD_LOGIC ;
		wrclk		: IN STD_LOGIC ;
		aclr		: IN STD_LOGIC  := '0';
		q		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
		rdfull		: OUT STD_LOGIC ;
		rdempty		: OUT STD_LOGIC ;
		wrfull		: OUT STD_LOGIC ;
		wrempty		: OUT STD_LOGIC 
	);
END fifo_data;


ARCHITECTURE RTL OF fifo_data IS

	ATTRIBUTE synthesis_clearbox: boolean;
	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
	SIGNAL sub_wire0	: STD_LOGIC ;
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;
	SIGNAL sub_wire3	: STD_LOGIC ;
	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (11 DOWNTO 0);



	COMPONENT fifo_data_dcfifo_9d01
	PORT (
			rdfull	: OUT STD_LOGIC ;
			wrclk	: IN STD_LOGIC ;
			rdempty	: OUT STD_LOGIC ;
			rdreq	: IN STD_LOGIC ;
			aclr	: IN STD_LOGIC ;
			wrfull	: OUT STD_LOGIC ;
			wrempty	: OUT STD_LOGIC ;
			rdclk	: IN STD_LOGIC ;
			q	: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
			wrreq	: IN STD_LOGIC ;
			data	: IN STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	rdfull    <= sub_wire0;
	rdempty    <= sub_wire1;
	wrfull    <= sub_wire2;
	wrempty    <= sub_wire3;
	q    <= sub_wire4(11 DOWNTO 0);

	fifo_data_dcfifo_9d01_component : fifo_data_dcfifo_9d01
	PORT MAP (
		wrclk => wrclk,
		rdreq => rdreq,
		aclr => aclr,
		rdclk => rdclk,
		wrreq => wrreq,
		data => data,
		rdfull => sub_wire0,
		rdempty => sub_wire1,
		wrfull => sub_wire2,
		wrempty => sub_wire3,
		q => sub_wire4
	);



END RTL;

-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: Width NUMERIC "12"
-- Retrieval info: PRIVATE: Depth NUMERIC "256"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "1"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: WIZMAN_OVERRIDE_CBX_GEN_MODE STRING "ON"
-- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "data;rdclk;rdreq;wrclk;wrreq"
-- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "aclr;q;rdempty;rdfull;wrempty"
-- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "wrfull;rdusedw;wrusedw"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
-- Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
-- Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=AUTO"
-- Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL data[11..0]
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-- Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
-- Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data_inst.vhd TRUE