------------------------------------------------------------------------------
-- Carte :		Cam-ass-ultra
-- Fonction : 	SAA signals decoder
-- Author :		crazyfred EIRBOT 2006
-- Date :		01.05.2006
------------------------------------------------------------------------------

library IEEE, work;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 
use work.all;

entity recorder is
	port (
		LLC2			: in std_logic;
		LLC				: in std_logic;

		start_recording : in std_logic;

		ram_granted		: in std_logic;

		pixel			: in std_logic_vector(31 downto 0);
		line_num		: in std_logic_vector(8 downto 0);
		pixel_num		: in std_logic_vector(9 downto 0);
		
		whichram		: in std_logic;
		
		request			: out std_logic;
		request_type	: out std_logic_vector(1 downto 0);
		recording		: out std_logic_vector(7 downto 0);
		Data			: inout std_logic_vector(15 downto 0);
		WR_L			: out std_logic;
		WR_H			: out std_logic;
		Address			: out std_logic_vector(18 downto 0);
		
		use_32_bits		: in std_logic

	);

end recorder;


architecture structure of recorder is

	signal recordstate		: std_logic_vector(1 downto 0);
	signal line_mul			: std_logic_vector(13 downto 0);
	signal contig_address	: std_logic_vector(17 downto 0);

	begin

	request_type <= '0'&whichram; -- ramV ou ramT

	recording(1 downto 0) <= recordstate;
	recording(4 downto 2) <= line_num(2 downto 0);
	recording(7 downto 5) <= pixel_num(2 downto 0);

	statemachine : process(LLC2, start_recording, ram_granted)
	begin
		if rising_edge(LLC2) then
			if start_recording = '1' and recordstate = "00" then
				recordstate <= "01"; -- demande d'acces
			elsif recordstate = "01" and ram_granted = '1' and line_num = "000000000" and pixel_num = "0000000001" then -- l=0, p=1
				recordstate <= "10"; -- acces autorise et debut de trame, on peut enregistrer
			elsif recordstate = "10" and line_num = "100011101"  and pixel_num="1011001111" then -- l=285, p=719
				recordstate <= "00"; -- fin de trame, c'est fini.
			elsif recordstate = "11" then
				recordstate <= "00"; -- etat a la con, on reset.
			end if;
		end if;
	end process;

	ram_request : process (recordstate)
	begin
		-- demande/maintient d'acces a la ram si on veut RECORD ou si on est entrain de RECORD
		if recordstate = "01" or recordstate = "10" then
			request <= '1';
		else
			request <= '0';
		end if;
	end process;

	sampling : process(LLC2, llc, line_num, pixel_num, pixel, recordstate)
	begin
		if recordstate /= "10" then
			Address <= "0000000000000000000";
			Data <= "ZZZZZZZZZZZZZZZZ";
		elsif rising_edge(LLC) then -- C'est pas grave si on utilise LLC au lieu de LLC2 lors d'un accés 16 bits, ce n'est que les bus, l'écriture ne se fait pas à cette vitesse
			if use_32_bits = '0' then
				Address <= '0'&contig_address;
				Data <= pixel(15 downto 0);
			else
				if LLC2 = '0' then
					Address <= contig_address&'0'; -- une chance sur deux que ce soit bien aligné dans la RAM
					Data <= pixel(15 downto 0);
				else
					Address <= contig_address&'1';
					Data <= pixel(31 downto 16);
				end if;
			end if;
		end if;
	end process;

	ram_access : process(recordstate, LLC2, llc, use_32_bits)
	begin
		if recordstate = "10" then -- on enregistre
			if use_32_bits = '0' then
				WR_L <= LLC2;
				WR_H <= LLC2;
			else
				WR_L <= LLC;
				WR_H <= LLC;
			end if;
		else
			WR_L <= '1';
			WR_H <= '1';
		end if;
	end process;

	-- 720 * line
	-- 720 = 16*45
	-- 45d = 101101b (32+8+4+1)
	line_mul <= (line_num&"00000") + ("00"&line_num&"000") + ("000"&line_num&"00") + ("00000"&line_num); -- 13 downto 0

	-- 720 * line + pixel
	contig_address <= (line_mul&"0000") + ("00000000"&pixel_num); -- 17 downto 0

-------------------------------------------------------------------------------
	end structure;