LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY quatre_lignes_rgb IS
	PORT (
		line_out 	: out	std_logic_vector(8 downto 0);
		pixel_out	: out	std_logic_vector(9 downto 0);

		r_out		: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
		v_out		: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
		b_out		: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);

		line_num 	: in	std_logic_vector(8 downto 0);
		pixel_num	: in	std_logic_vector(9 downto 0);

		r			: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
		v			: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
		b			: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);

		clock		: in	std_logic;
		
		coeff_0_A	: in	std_logic_vector(7 downto 0);
		coeff_1_A	: in	std_logic_vector(7 downto 0);
		coeff_2_A	: in	std_logic_vector(7 downto 0);
		coeff_0_B	: in	std_logic_vector(7 downto 0);
		coeff_1_B	: in	std_logic_vector(7 downto 0);
		coeff_2_B	: in	std_logic_vector(7 downto 0);
		coeff_0_C	: in	std_logic_vector(7 downto 0);
		coeff_1_C	: in	std_logic_vector(7 downto 0);
		coeff_2_C	: in	std_logic_vector(7 downto 0)
	);

END quatre_lignes_rgb ;

ARCHITECTURE a OF quatre_lignes_rgb IS

component multiply3_8x8_add
	PORT
	(
		clock0		: IN STD_LOGIC  := '1';
		dataa_0		: IN STD_LOGIC_VECTOR (7 DOWNTO 0) :=  (OTHERS => '0');
		dataa_1		: IN STD_LOGIC_VECTOR (7 DOWNTO 0) :=  (OTHERS => '0');
		datab_0		: IN STD_LOGIC_VECTOR (7 DOWNTO 0) :=  (OTHERS => '0');
		dataa_2		: IN STD_LOGIC_VECTOR (7 DOWNTO 0) :=  (OTHERS => '0');
		datab_1		: IN STD_LOGIC_VECTOR (7 DOWNTO 0) :=  (OTHERS => '0');
		datab_2		: IN STD_LOGIC_VECTOR (7 DOWNTO 0) :=  (OTHERS => '0');
		result		: OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
	);
end component;

component une_ligne
	PORT (
		clock		: in	std_logic;
		
		wren		: in	std_logic;
		pixel_num	: in	std_logic_vector(9 downto 0);

		data_sig	: IN	STD_LOGIC_VECTOR(23 DOWNTO 0);
		
		q_n		: out	STD_LOGIC_VECTOR(23 DOWNTO 0); -- q(addr)
		q_n1	: out	STD_LOGIC_VECTOR(23 DOWNTO 0); -- q(addr+1)
		q_n2	: out	STD_LOGIC_VECTOR(23 DOWNTO 0); -- q(addr+2)
		q_n3	: out	STD_LOGIC_VECTOR(23 DOWNTO 0)  -- q(addr+3)
	);
END component ;

signal q_n_A, q_n1_A, q_n2_A, q_n3_A : std_logic_vector(23 downto 0);
signal q_n_B, q_n1_B, q_n2_B, q_n3_B : std_logic_vector(23 downto 0);
signal q_n_C, q_n1_C, q_n2_C, q_n3_C : std_logic_vector(23 downto 0);
signal q_n_D, q_n1_D, q_n2_D, q_n3_D : std_logic_vector(23 downto 0);
signal wren_A, wren_B, wren_C, wren_D : std_logic;

signal d_n_A, d_n1_A, d_n2_A, d_n3_A : std_logic_vector(23 downto 0);
signal d_n_B, d_n1_B, d_n2_B, d_n3_B : std_logic_vector(23 downto 0);
signal d_n_C, d_n1_C, d_n2_C, d_n3_C : std_logic_vector(23 downto 0);

signal entree : std_logic_vector(23 downto 0);

signal lineAr_mul, lineBr_mul, lineCr_mul : std_logic_vector(17 downto 0);
signal lineAv_mul, lineBv_mul, lineCv_mul : std_logic_vector(17 downto 0);
signal lineAb_mul, lineBb_mul, lineCb_mul : std_logic_vector(17 downto 0);

signal r_filt, v_filt, b_filt : std_logic_vector(19 downto 0);

BEGIN

entree <= r(7 downto 0)&v(7 downto 0)&b(7 downto 0);

-- l'entree est envoyee vers un des 4 buffers de lignes
-- 3 sont en lecture et 1 est en écriture
wren_A   <= not line_num(0) and not line_num(1);  -- A
wren_B   <=     line_num(0) and not line_num(1);  -- B
wren_C   <= not line_num(0) and     line_num(1);  -- C
wren_D   <=     line_num(0) and     line_num(1);  -- D

-- on recupere 12 pixels (3 lignes de 4 pixels)

selection : process(line_num, q_n_A, q_n1_A, q_n2_A, q_n3_A, q_n_B, q_n1_B, q_n2_B, q_n3_B, q_n_C, q_n1_C, q_n2_C, q_n3_C, q_n_D, q_n1_D, q_n2_D, q_n3_D)
begin
	case line_num(1 downto 0) is
		when "00" =>
			d_n_A <= q_n_B; d_n1_A <= q_n1_B; d_n2_A <= q_n2_B; d_n3_A <= q_n3_B;
			d_n_B <= q_n_C; d_n1_B <= q_n1_C; d_n2_B <= q_n2_C; d_n3_B <= q_n3_C;
			d_n_C <= q_n_D; d_n1_C <= q_n1_D; d_n2_C <= q_n2_D; d_n3_C <= q_n3_D;
		when "01" =>
			d_n_A <= q_n_C; d_n1_A <= q_n1_C; d_n2_A <= q_n2_C; d_n3_A <= q_n3_C;
			d_n_B <= q_n_D; d_n1_B <= q_n1_D; d_n2_B <= q_n2_D; d_n3_B <= q_n3_D;
			d_n_C <= q_n_A; d_n1_C <= q_n1_A; d_n2_C <= q_n2_A; d_n3_C <= q_n3_A;
		when "10" =>
			d_n_A <= q_n_D; d_n1_A <= q_n1_D; d_n2_A <= q_n2_D; d_n3_A <= q_n3_D;
			d_n_B <= q_n_A; d_n1_B <= q_n1_A; d_n2_B <= q_n2_A; d_n3_B <= q_n3_A;
			d_n_C <= q_n_B; d_n1_C <= q_n1_B; d_n2_C <= q_n2_B; d_n3_C <= q_n3_B;
		when "11" =>
			d_n_A <= q_n_A; d_n1_A <= q_n1_A; d_n2_A <= q_n2_A; d_n3_A <= q_n3_A;
			d_n_B <= q_n_B; d_n1_B <= q_n1_B; d_n2_B <= q_n2_B; d_n3_B <= q_n3_B;
			d_n_C <= q_n_C; d_n1_C <= q_n1_C; d_n2_C <= q_n2_C; d_n3_C <= q_n3_C;
	end case;
end process;

r_filt <= ("00"&lineAr_mul) + ("00"&lineBr_mul) + ("00"&lineCr_mul);
v_filt <= ("00"&lineAv_mul) + ("00"&lineBv_mul) + ("00"&lineCv_mul);
b_filt <= ("00"&lineAb_mul) + ("00"&lineBb_mul) + ("00"&lineCb_mul);

synchroclock : process(clock)
begin
	if (rising_edge(clock)) then
		line_out <= line_num;
		pixel_out <= pixel_num;
		
		if r_filt(19 downto 14) = "000000" then
			r_out <= r_filt(13 downto 6);
		elsif r_filt(19) = '1' then -- négatif
			r_out <= "00000000";
		else -- positif mais trop grand
			r_out <= "11111111";
		end if;

		if v_filt(19 downto 14) = "000000" then
			v_out <= v_filt(13 downto 6);
		elsif v_filt(19) = '1' then -- négatif
			v_out <= "00000000";
		else -- positif mais trop grand
			v_out <= "11111111";
		end if;

		if b_filt(19 downto 14) = "000000" then
			b_out <= b_filt(13 downto 6);
		elsif r_filt(19) = '1' then -- négatif
			b_out <= "00000000";
		else -- positif mais trop grand
			b_out <= "11111111";
		end if;

	end if;
end process;

multiply3_lineA_r : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_A(23 downto 16),
		dataa_1	 => d_n1_A(23 downto 16),
		dataa_2	 => d_n2_A(23 downto 16),
		datab_0	 => coeff_0_A,
		datab_1	 => coeff_1_A,
		datab_2	 => coeff_2_A,
		result	 => lineAr_mul
	);

multiply3_lineB_r : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_B(23 downto 16),
		dataa_1	 => d_n1_B(23 downto 16),
		dataa_2	 => d_n2_B(23 downto 16),
		datab_0	 => coeff_0_B,
		datab_1	 => coeff_1_B,
		datab_2	 => coeff_2_B,
		result	 => lineBr_mul
	);

multiply3_lineC_r : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_C(23 downto 16),
		dataa_1	 => d_n1_C(23 downto 16),
		dataa_2	 => d_n2_C(23 downto 16),
		datab_0	 => coeff_0_C,
		datab_1	 => coeff_1_C,
		datab_2	 => coeff_2_C,
		result	 => lineCr_mul
	);

multiply3_lineA_v : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_A(15 downto 8),
		dataa_1	 => d_n1_A(15 downto 8),
		dataa_2	 => d_n2_A(15 downto 8),
		datab_0	 => coeff_0_A,
		datab_1	 => coeff_1_A,
		datab_2	 => coeff_2_A,
		result	 => lineAv_mul
	);

multiply3_lineB_v : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_B(15 downto 8),
		dataa_1	 => d_n1_B(15 downto 8),
		dataa_2	 => d_n2_B(15 downto 8),
		datab_0	 => coeff_0_B,
		datab_1	 => coeff_1_B,
		datab_2	 => coeff_2_B,
		result	 => lineBv_mul
	);

multiply3_lineC_v : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_C(15 downto 8),
		dataa_1	 => d_n1_C(15 downto 8),
		dataa_2	 => d_n2_C(15 downto 8),
		datab_0	 => coeff_0_C,
		datab_1	 => coeff_1_C,
		datab_2	 => coeff_2_C,
		result	 => lineCv_mul
	);

multiply3_lineA_b : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_A(7 downto 0),
		dataa_1	 => d_n1_A(7 downto 0),
		dataa_2	 => d_n2_A(7 downto 0),
		datab_0	 => coeff_0_A,
		datab_1	 => coeff_1_A,
		datab_2	 => coeff_2_A,
		result	 => lineAb_mul
	);

multiply3_lineB_b : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_B(7 downto 0),
		dataa_1	 => d_n1_B(7 downto 0),
		dataa_2	 => d_n2_B(7 downto 0),
		datab_0	 => coeff_0_B,
		datab_1	 => coeff_1_B,
		datab_2	 => coeff_2_B,
		result	 => lineBb_mul
	);

multiply3_lineC_b : multiply3_8x8_add PORT MAP (
		clock0	 => clock,
		dataa_0	 => d_n_C(7 downto 0),
		dataa_1	 => d_n1_C(7 downto 0),
		dataa_2	 => d_n2_C(7 downto 0),
		datab_0	 => coeff_0_C,
		datab_1	 => coeff_1_C,
		datab_2	 => coeff_2_C,
		result	 => lineCb_mul
	);

ligne_A : une_ligne PORT MAP
	(
		clock => clock,
		wren  => wren_A,
		pixel_num => pixel_num,
		data_sig => entree,
		q_n => q_n_A,
		q_n1 => q_n1_A,
		q_n2 => q_n2_A,
		q_n3 => q_n3_A
	);
ligne_B : une_ligne PORT MAP
	(
		clock => clock,
		wren  => wren_B,
		pixel_num => pixel_num,
		data_sig => entree,
		q_n => q_n_B,
		q_n1 => q_n1_B,
		q_n2 => q_n2_B,
		q_n3 => q_n3_B
	);
ligne_C : une_ligne PORT MAP
	(
		clock => clock,
		wren  => wren_C,
		pixel_num => pixel_num,
		data_sig => entree,
		q_n => q_n_C,
		q_n1 => q_n1_C,
		q_n2 => q_n2_C,
		q_n3 => q_n3_C
	);
ligne_D : une_ligne PORT MAP
	(
		clock => clock,
		wren  => wren_D,
		pixel_num => pixel_num,
		data_sig => entree,
		q_n => q_n_D,
		q_n1 => q_n1_D,
		q_n2 => q_n2_D,
		q_n3 => q_n3_D
	);

END a;