LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY seuillage IS
  
	PORT (
		code_out    : OUT integer range 0 to 7;

		regl_in		: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
		regl_sel	: IN	STD_LOGIC_VECTOR(5 DOWNTO 0);
		regl_write	: IN	STD_LOGIC;

		H_in		: IN	STD_LOGIC_VECTOR(10 DOWNTO 0);
		S_in		: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
		L_in		: IN	STD_LOGIC_VECTOR(8 DOWNTO 0);
		
		clock		: IN	std_logic
	);

END seuillage ;

ARCHITECTURE a OF seuillage IS

	signal h0_min, h0_max, h1_min, h1_max, h2_min, h2_max, h3_min, h3_max : std_logic_vector(10 downto 0);
	signal h4_min, h4_max, h5_min, h5_max, h6_min, h6_max, h7_min, h7_max : std_logic_vector(10 downto 0);

	signal s0_min, s0_max, s1_min, s1_max, s2_min, s2_max, s3_min, s3_max : std_logic_vector(7 downto 0);
	signal s4_min, s4_max, s5_min, s5_max, s6_min, s6_max, s7_min, s7_max : std_logic_vector(7 downto 0);

	signal l0_min, l0_max, l1_min, l1_max, l2_min, l2_max, l3_min, l3_max : std_logic_vector(8 downto 0);
	signal l4_min, l4_max, l5_min, l5_max, l6_min, l6_max, l7_min, l7_max : std_logic_vector(8 downto 0);

	signal H : std_logic_vector(10 downto 0);
	signal S : std_logic_vector(7 downto 0);
	signal L : std_logic_vector(8 downto 0);

BEGIN

	registring : process(clock, H_in, S_in, L_in)
	begin
		if rising_edge(clock) then
			H <= H_in;
			S <= S_in;
			L <= L_in;
		end if;
	end process;

	regl_seuils: process(regl_in, regl_sel, regl_write)
	begin
		if regl_write = '1' then
		case regl_sel is
			when "000000" => h0_min <= regl_in(10 downto 0);
			when "000001" => h0_max <= regl_in(10 downto 0);
			when "000010" => s0_min <= regl_in(7 downto 0);
			when "000011" => s0_max <= regl_in(7 downto 0);
			when "000100" => l0_min <= regl_in(8 downto 0);
			when "000101" => l0_max <= regl_in(8 downto 0);

			when "001000" => h1_min <= regl_in(10 downto 0);
			when "001001" => h1_max <= regl_in(10 downto 0);
			when "001010" => s1_min <= regl_in(7 downto 0);
			when "001011" => s1_max <= regl_in(7 downto 0);
			when "001100" => l1_min <= regl_in(8 downto 0);
			when "001101" => l1_max <= regl_in(8 downto 0);

			when "010000" => h2_min <= regl_in(10 downto 0);
			when "010001" => h2_max <= regl_in(10 downto 0);
			when "010010" => s2_min <= regl_in(7 downto 0);
			when "010011" => s2_max <= regl_in(7 downto 0);
			when "010100" => l2_min <= regl_in(8 downto 0);
			when "010101" => l2_max <= regl_in(8 downto 0);

			when "011000" => h3_min <= regl_in(10 downto 0);
			when "011001" => h3_max <= regl_in(10 downto 0);
			when "011010" => s3_min <= regl_in(7 downto 0);
			when "011011" => s3_max <= regl_in(7 downto 0);
			when "011100" => l3_min <= regl_in(8 downto 0);
			when "011101" => l3_max <= regl_in(8 downto 0);

			when "100000" => h4_min <= regl_in(10 downto 0);
			when "100001" => h4_max <= regl_in(10 downto 0);
			when "100010" => s4_min <= regl_in(7 downto 0);
			when "100011" => s4_max <= regl_in(7 downto 0);
			when "100100" => l4_min <= regl_in(8 downto 0);
			when "100101" => l4_max <= regl_in(8 downto 0);

			when "101000" => h5_min <= regl_in(10 downto 0);
			when "101001" => h5_max <= regl_in(10 downto 0);
			when "101010" => s5_min <= regl_in(7 downto 0);
			when "101011" => s5_max <= regl_in(7 downto 0);
			when "101100" => l5_min <= regl_in(8 downto 0);
			when "101101" => l5_max <= regl_in(8 downto 0);

			when "110000" => h6_min <= regl_in(10 downto 0);
			when "110001" => h6_max <= regl_in(10 downto 0);
			when "110010" => s6_min <= regl_in(7 downto 0);
			when "110011" => s6_max <= regl_in(7 downto 0);
			when "110100" => l6_min <= regl_in(8 downto 0);
			when "110101" => l6_max <= regl_in(8 downto 0);

--			when "111000" => h7_min <= regl_in(8 downto 0);
--			when "111001" => h7_max <= regl_in(8 downto 0);
--			when "111010" => s7_min <= regl_in(6 downto 0);
--			when "111011" => s7_max <= regl_in(6 downto 0);
--			when "111100" => l7_min <= regl_in(5 downto 0);
--			when "111101" => l7_max <= regl_in(5 downto 0);
			
			when others => NULL;
		end case;
		end if;
	end process regl_seuils;
	
multi_seuil:
PROCESS (H, S, L, h0_min, h0_max, s0_min, s0_max, l0_min, l0_max, 
		h1_min, h1_max, s1_min, s1_max, l1_min, l1_max, 
		h2_min, h2_max, s2_min, s2_max, l2_min, l2_max, 
		h3_min, h3_max, s3_min, s3_max, l3_min, l3_max,
		h4_min, h4_max, s4_min, s4_max, l4_min, l4_max,
		h5_min, h5_max, s5_min, s5_max, l5_min, l5_max,
		h6_min, h6_max, s6_min, s6_max, l6_min, l6_max)
BEGIN
		if h0_min <= H and H <= h0_max and s0_min <= S and S <= s0_max and l0_min <= L and L <= l0_max then
			code_out <= 0;
		elsif h1_min <= H and H <= h1_max and s1_min <= S and S <= s1_max and l1_min <= L and L <= l1_max then
			code_out <= 1;
		elsif h2_min <= H and H <= h2_max and s2_min <= S and S <= s2_max and l2_min <= L and L <= l2_max then
			code_out <= 2;
		elsif h3_min <= H and H <= h3_max and s3_min <= S and S <= s3_max and l3_min <= L and L <= l3_max then
			code_out <= 3;
		elsif h4_min <= H and H <= h4_max and s4_min <= S and S <= s4_max and l4_min <= L and L <= l4_max then
			code_out <= 4;
		elsif h5_min <= H and H <= h5_max and s5_min <= S and S <= s5_max and l5_min <= L and L <= l5_max then
			code_out <= 5;
		elsif h6_min <= H and H <= h6_max and s6_min <= S and S <= s6_max and l6_min <= L and L <= l6_max then
			code_out <= 6;
--		elsif h7_min <= H and H <= h7_max and s7_min <= S and S <= s7_max and l7_min <= L and L <= l7_max then
--			code_out <= 7;
		else
			code_out <= 7;
		end if;
END PROCESS multi_seuil;

END a;