------------------------------------------------------------------------------
-- Affaire :   ROBOT
-- Carte :		Cam-ass-ultra
-- Fonction : 	génération des signaux pour la tv
-- Author :		Eirbot 2006 / crazyfred
-- Date :		12.05.2006
------------------------------------------------------------------------------

library IEEE, work;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 
use work.all;

entity display is
	port (
		sync_a   : in std_logic;
		blank_a  : in std_logic;
		burst_a  : in std_logic;
		code_a : in std_logic_vector(2 downto 0);
		hue_a : in std_logic_vector(10 downto 0);
		sat_a : in std_logic_vector(7 downto 0);
		light_a : in std_logic_vector(8 downto 0);
		cvbs_a : in std_logic_vector(7 downto 0);
		row_a : in std_logic_vector(9 downto 0);
		line_a : in std_logic_vector(8 downto 0);

		sync_b   : in std_logic;
		blank_b  : in std_logic;
		burst_b  : in std_logic;
		code_b : in std_logic_vector(2 downto 0);
		hue_b : in std_logic_vector(10 downto 0);
		sat_b : in std_logic_vector(7 downto 0);
		light_b : in std_logic_vector(8 downto 0);
		cvbs_b : in std_logic_vector(7 downto 0);
		row_b : in std_logic_vector(9 downto 0);
		line_b : in std_logic_vector(8 downto 0);

		test : in std_logic_vector(7 downto 0);
		sw : in std_logic_vector(7 downto 0);
		pos_x : in std_logic_vector(7 downto 0);
		pos_y : in std_logic_vector(7 downto 0);

		bit7  : out std_logic;
		bit6  : out std_logic;
		bit5  : out std_logic;
		bit4  : out std_logic;
		bit3  : out std_logic;
		bit2  : out std_logic;
		bit1  : out std_logic;
		bit0  : out std_logic;

		clk : in std_logic;
		q_overlay_ram : out std_logic_vector(7 downto 0);
		d_overlay_ram : in std_logic_vector(7 downto 0);
		a_overlay_ram : in std_logic_vector(12 downto 0);
		wren_overlay_ram : in std_logic
	);

end display;


architecture structure of display is

signal outbits : std_logic_vector(7 downto 0);
signal selected : std_logic_vector(7 downto 0);
signal overlayed : std_logic_vector(7 downto 0);
signal row : std_logic_vector(9 downto 0);
signal line : std_logic_vector(8 downto 0);
signal q_b : std_logic_vector(0 downto 0);
signal a_overlay : std_logic_vector(15 downto 0);

component ram_overlay
	PORT
	(
		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren_a		: IN STD_LOGIC  := '1';
		address_a		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		data_b		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
		address_b		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		wren_b		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		q_b		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
	);
end component;

	begin

	bit0 <= outbits(0);
	bit1 <= outbits(1);
	bit2 <= outbits(2);
	bit3 <= outbits(3);
	bit4 <= outbits(4);
	bit5 <= outbits(5);
	bit6 <= outbits(6);
	bit7 <= outbits(7);

-------------------------------------------------------------------------------
-- sw(7) : cam a(0) ou cam b(1)
-- sw(6) : enable cross (inverse couleur)
-- sw(5 downto 4) : "01" overlay = noir, "11" overlay = blanc, "10" overlay = inverse couleur
-- sw(3) : enable color
-- sw(2 downto 0) : mode d'affichage
-------------------------------------------------------------------------------

	process (test, sync_a, sync_b, blank_a, blank_b, selected, sw, overlayed, burst_a, burst_b)
	begin
		if sw /= "11111111" then
			if (sync_a = '1' and sw(7) = '0') or (sync_b = '1' and sw(7) = '1') then
				outbits <= "00000000";
			elsif (blank_a = '1' and sw(7) = '0' and not(sw(3) = '1' and burst_a = '1')) or (blank_b = '1' and sw(7) = '1' and not(sw(3) = '1' and burst_b = '1')) then
				outbits <= "01001101";
			elsif (sw(7) = '0' and sw(3) = '1' and burst_a = '1') or (sw(7) = '1' and sw(3) = '1' and burst_b = '1') then -- le burst
				-- attention au bit de signe
				outbits <= (overlayed(7)&overlayed(7 downto 1)) + (overlayed(7)&overlayed(7)&overlayed(7)&overlayed(7 downto 3)) + (overlayed(7)&overlayed(7)&overlayed(7)&overlayed(7)&overlayed(7 downto 4)) + "01001101"; -- mise a l'echelle entre 0.375 et 1
			else
				outbits <= ('0'&overlayed(7 downto 1)) + ("000"&overlayed(7 downto 3)) + ("0000"&overlayed(7 downto 4)) + "01001101"; -- mise a l'echelle entre 0.375 et 1
			end if;
		else
			outbits <= test;
		end if;
	end process;

-------------------------------------------------------------------------------

	process (sw, code_a, hue_a, sat_a, light_a, code_b, hue_b, sat_b, light_b, cvbs_a, cvbs_b)
	begin
		case sw(3 downto 0) is
			when "0000" => selected <= code_a&"00000";
			when "0001" => selected <= hue_a(10 downto 3);
			when "0010" => selected <= sat_a;
			when "0011" => selected <= light_a(8 downto 1);
			when "1000" => selected <= cvbs_a;

			when "0100" => selected <= code_b&"00000";
			when "0101" => selected <= hue_b(10 downto 3);
			when "0110" => selected <= sat_b;
			when "0111" => selected <= light_b(8 downto 1);
			when "1100" => selected <= cvbs_b;

			when others => selected <= "00000000";
		end case;
	end process;

-------------------------------------------------------------------------------

	process(sw, line_a,line_b, row_a,row_b,sw)
	begin
		if sw(7) = '0' then
			line <= line_a;
			row  <= row_a;
		else
			line <= line_b;
			row  <= row_b;
		end if;
	end process;

-------------------------------------------------------------------------------

	overlay : process(selected, row, line, pos_x,pos_y,sw, q_b)
	begin
		if (sw(6) = '1' and ((row(9 downto 2) = pos_x) or (line(8 downto 1) = pos_y))) then
			overlayed <= not(selected);
		elsif (sw(5 downto 4) = "01" and q_b = "1") then
			overlayed <= "00000000";
		elsif (sw(5 downto 4) = "11" and q_b = "1") then
			overlayed <= "11111111";
		elsif (sw(5 downto 4) = "10" and q_b = "1") then
			overlayed <= not(selected);
		else
			overlayed <= selected;
		end if;
	end process;

-------------------------------------------------------------------------------
a_overlay <= line(8 downto 1)&row(9 downto 2);

ram_overlay_inst : ram_overlay PORT MAP (
		clock		=> clk,

		data_b		=> "0",
		wren_b		=> '0',
		address_b	=> a_overlay,
		q_b			=> q_b,

		data_a		=> d_overlay_ram,
		address_a	=> a_overlay_ram,
		wren_a		=> wren_overlay_ram,
		q_a			=> q_overlay_ram
	);

	end structure;