library IEEE, work;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 
use work.all;

entity multi8_tb is
	port (
		s_line_num_out  : out integer range 0 to 511;
		s_pixel_num_out : out integer range 0 to 1023;
		s_code_out      : out integer range 0 to 7;
		s_blank_out     : out std_logic;
		s_sync_out      : out std_logic;
		s_win_out       : out std_logic
	);

end multi8_tb;


architecture structure of multi8_tb is

component saa_decode is
	port (
		LLC2      : in std_logic;
		RESETn    : in std_logic;

		HS        : in std_logic;	-- SAA: synchro trame
		VS        : in std_logic;	-- SAA: synchro ligne
		HREF      : in std_logic;	-- SAA: pixels actifs
		VREF      : in std_logic;

		line_num  : out std_logic_vector(8 downto 0);
		pixel_num : out std_logic_vector(9 downto 0);

		RTS0      : in std_logic;
		
		blank     : out std_logic;
		sync      : out std_logic;
		image     : out std_logic
	);
	end component;

component fenetre IS

	PORT (
		cpt_line	: IN  integer range 0 to 511;
		cpt_row	    : IN  integer range 0 to 1023;

		win      : OUT std_logic;
		end_of_frame : out std_logic
	);

END component;

component multi8_palet IS
  
	PORT (
		line_in		: IN  integer range 0 to 511;
		row_in	    : IN  integer range 0 to 1023;

		row_out		: OUT integer range 0 to 1023;
		line_out	: OUT integer range 0 to 511;

		code_out    : OUT integer range 0 to 7;
		code_in     : IN  integer range 0 to 7;

		choix_in	: IN  std_logic_vector(7 downto 0);
		donnee      : OUT std_logic_vector(11 downto 0);
    
		win_in		: IN  std_logic;
		win_out		: OUT std_logic;

		blank_in    : in std_logic;
		sync_in     : in std_logic;
		blank_out   : out std_logic;
		sync_out    : out std_logic;

		reset_n     : IN  std_logic;
		clock       : IN  std_logic;

		code_detect : in integer range 0 to 7;
		code_ok     : in integer range 0 to 7;

		seuilpixel  : in integer range 0 to 15;
		seuilligne  : in integer range 0 to 15;
		
		write_code  : in std_logic;
		select_code : in std_logic_vector(5 downto 0)
	);

END component;

	signal sLLC2 : std_logic;
	signal sRESETn : std_logic;
	signal sHS : std_logic;
	signal sVS : std_logic;
	signal sVREF : std_logic;
	signal sHREF : std_logic;
	signal sRTS0 : std_logic;
	
	signal s_line_num  : std_logic_vector(8 downto 0);
	signal s_pixel_num : std_logic_vector(9 downto 0);
	signal s_line_num_i  : integer range 0 to 511;
	signal s_pixel_num_i : integer range 0 to 1023;
	signal s_blank     : std_logic;
	signal s_sync      : std_logic;
	signal s_image     : std_logic;

	signal s_win,eof : std_logic;
	signal s_code      : integer range 0 to 7;

	signal s_donnee    : std_logic_vector(11 downto 0);
	signal s_config    : std_logic_vector(5 downto 0);

	signal s_choix	: std_logic_vector(7 downto 0);

	begin

test : saa_decode 
	PORT MAP
	(
		LLC2 => sLLC2,
		RESETn => sRESETn,
		HS => sHS,
		VS => sVS,
		HREF => sHREF,
		VREF => sVREF,
		line_num => s_line_num,
		pixel_num => s_pixel_num,
		RTS0 => sRTS0,
		blank => s_blank,
		sync => s_sync,
		image => s_image
	);

window: fenetre
	PORT MAP
	(
		cpt_line => s_line_num_i,
		cpt_row => s_pixel_num_i,
		win => s_win,
		end_of_frame => eof
	);


multipal: multi8_palet  
	PORT MAP
	(
		line_in => s_line_num_i,
		row_in => s_pixel_num_i,
		row_out => s_pixel_num_out,
		line_out => s_line_num_out,
		code_out => s_code_out,
		code_in => s_code,
		choix_in => s_choix,
		donnee => s_donnee,
		win_in => s_win,
		win_out => s_win_out,
		blank_in => s_blank,
		sync_in => s_sync,
		blank_out => s_blank_out,
		sync_out => s_sync_out,
		reset_n => sRESETn,
		clock => sLLC2,
		code_detect => 0,
		code_ok => 7,
		seuilpixel => 7,
		seuilligne => 7,
		write_code => sLLC2,
		select_code => s_config
	);

s_line_num_i <= to_integer(unsigned(s_line_num));
s_pixel_num_i <= to_integer(unsigned(s_pixel_num));

-------------------------------------------------------------------------------
	codeur : process(s_line_num, s_pixel_num)
	begin
		if (s_line_num < 40 and s_line_num > 30 and s_pixel_num < 40 and s_pixel_num > 30) or (s_line_num < 70 and s_line_num > 60 and s_pixel_num < 100 and s_pixel_num > 90) then
			s_code <= 0;
		else
			s_code <= 1;
		end if;
	end process;
-------------------------------------------------------------------------------
	horloge : process
	begin
		sLLC2 <= '0', '1' after 0.5 us;
		wait for 1 us;
	end process;
-------------------------------------------------------------------------------
	sRESETn <= '1';
	sHS <= '0';
	sVS <= '1';
-------------------------------------------------------------------------------
	horiz : process
	begin
		sHREF <= '0', '1' after 144 us;
		wait for 864 us;
	end process;
-------------------------------------------------------------------------------
	verti : process
	begin
		sVREF <= '0', '1' after 11232 us;
		wait for 112320 us;
	end process;
-------------------------------------------------------------------------------
	field : process
	begin
		sRTS0 <= '0', '1' after 112320 us;
		wait for 224640 us;
	end process;
-------------------------------------------------------------------------------
--	config : process
--	begin
		s_config <= "000000";
--	end process;
-------------------------------------------------------------------------------
	s_choix <= s_pixel_num(8 downto 1);
-------------------------------------------------------------------------------

	end structure;