-- megafunction wizard: %ALTMULT_ADD% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: ALTMULT_ADD -- ============================================================ -- File Name: multiply3_8x8_add.vhd -- Megafunction Name(s): -- ALTMULT_ADD -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 4.0 Build 190 1/28/2004 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2004 Altera Corporation --Any megafunction design, and related netlist (encrypted or decrypted), --support information, device programming or simulation file, and any other --associated documentation or information provided by Altera or a partner --under Altera's Megafunction Partnership Program may be used only --to program PLD devices (but not masked PLD devices) from Altera. Any --other use of such megafunction design, netlist, support information, --device programming or simulation file, or any other related documentation --or information is prohibited for any other purpose, including, but not --limited to modification, reverse engineering, de-compiling, or use with --any other silicon devices, unless such use is explicitly licensed under --a separate agreement with Altera or a megafunction partner. Title to the --intellectual property, including patents, copyrights, trademarks, trade --secrets, or maskworks, embodied in any such megafunction design, netlist, --support information, device programming or simulation file, or any other --related documentation or information provided by Altera or a megafunction --partner, remains with Altera, the megafunction partner, or their respective --licensors. No other licenses, including any licenses needed under any third --party's intellectual property, are provided herein. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY multiply3_8x8_add IS PORT ( clock0 : IN STD_LOGIC := '1'; dataa_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0'); dataa_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0'); datab_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0'); dataa_2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0'); datab_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0'); datab_2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0'); result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END multiply3_8x8_add; ARCHITECTURE SYN OF multiply3_8x8_add IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC_VECTOR (23 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire6 : STD_LOGIC_VECTOR (23 DOWNTO 0); SIGNAL sub_wire7 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire8 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altmult_add GENERIC ( input_register_b2 : STRING; input_register_a1 : STRING; multiplier_register0 : STRING; signed_pipeline_aclr_b : STRING; input_register_a2 : STRING; multiplier_register1 : STRING; addnsub_multiplier_pipeline_aclr1 : STRING; multiplier_register2 : STRING; signed_register_a : STRING; number_of_multipliers : NATURAL; multiplier_aclr0 : STRING; signed_register_b : STRING; lpm_type : STRING; multiplier_aclr1 : STRING; output_register : STRING; width_result : NATURAL; representation_a : STRING; signed_pipeline_register_a : STRING; input_source_b0 : STRING; multiplier_aclr2 : STRING; addnsub_multiplier_register1 : STRING; representation_b : STRING; signed_pipeline_register_b : STRING; input_source_b1 : STRING; input_source_a0 : STRING; dedicated_multiplier_circuitry : STRING; input_source_b2 : STRING; input_source_a1 : STRING; input_source_a2 : STRING; intended_device_family : STRING; addnsub_multiplier_pipeline_register1 : STRING; width_a : NATURAL; input_register_b0 : STRING; width_b : NATURAL; input_register_b1 : STRING; input_register_a0 : STRING; multiplier1_direction : STRING; signed_pipeline_aclr_a : STRING ); PORT ( dataa : IN STD_LOGIC_VECTOR (23 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (23 DOWNTO 0); clock0 : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(15 DOWNTO 0); sub_wire1 <= dataa_0(7 DOWNTO 0); sub_wire3 <= dataa_1(7 DOWNTO 0); sub_wire4 <= dataa_2(7 DOWNTO 0); sub_wire2 <= sub_wire4(7 DOWNTO 0) & sub_wire3(7 DOWNTO 0) & sub_wire1(7 DOWNTO 0); sub_wire5 <= datab_1(7 DOWNTO 0); sub_wire7 <= datab_0(7 DOWNTO 0); sub_wire8 <= datab_2(7 DOWNTO 0); sub_wire6 <= sub_wire8(7 DOWNTO 0) & sub_wire5(7 DOWNTO 0) & sub_wire7(7 DOWNTO 0); ALTMULT_ADD_component : altmult_add GENERIC MAP ( input_register_b2 => "UNREGISTERED", input_register_a1 => "UNREGISTERED", multiplier_register0 => "CLOCK0", signed_pipeline_aclr_b => "UNUSED", input_register_a2 => "UNREGISTERED", multiplier_register1 => "CLOCK0", addnsub_multiplier_pipeline_aclr1 => "UNUSED", multiplier_register2 => "CLOCK0", signed_register_a => "UNREGISTERED", number_of_multipliers => 3, multiplier_aclr0 => "UNUSED", signed_register_b => "UNREGISTERED", lpm_type => "altmult_add", multiplier_aclr1 => "UNUSED", output_register => "UNREGISTERED", width_result => 16, representation_a => "UNSIGNED", signed_pipeline_register_a => "CLOCK0", input_source_b0 => "DATAB", multiplier_aclr2 => "UNUSED", addnsub_multiplier_register1 => "UNREGISTERED", representation_b => "SIGNED", signed_pipeline_register_b => "CLOCK0", input_source_b1 => "DATAB", input_source_a0 => "DATAA", dedicated_multiplier_circuitry => "AUTO", input_source_b2 => "DATAB", input_source_a1 => "DATAA", input_source_a2 => "DATAA", intended_device_family => "Stratix", addnsub_multiplier_pipeline_register1 => "CLOCK0", width_a => 8, input_register_b0 => "UNREGISTERED", width_b => 8, input_register_b1 => "UNREGISTERED", input_register_a0 => "UNREGISTERED", multiplier1_direction => "ADD", signed_pipeline_aclr_a => "UNUSED" ) PORT MAP ( dataa => sub_wire2, datab => sub_wire6, clock0 => clock0, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input" -- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "0" -- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: SIGNA STRING "Unsigned" -- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15" -- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNB STRING "Signed" -- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1" -- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0" -- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0" -- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0" -- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: RTS_WIDTH STRING "16" -- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0" -- Retrieval info: PRIVATE: NUM_MULT STRING "3" -- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "dataa;datab;addnsub1;addnsub3;signa" -- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0" -- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "signb;clock0;clock1;clock2;clock3" -- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0" -- Retrieval info: PRIVATE: REG_OUT NUMERIC "0" -- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "ena0;ena1;ena2;ena3;aclr0" -- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "aclr1;aclr2;aclr3;scanina;scaninb" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1" -- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "sourcea;sourceb;mult01_round;mult23_round;mult01_saturation" -- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_5 STRING "mult23_saturation;addnsub1_round;addnsub3_round;result;scanouta" -- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNA_REG STRING "0" -- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0" -- Retrieval info: PRIVATE: WIDTHA STRING "8" -- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_6 STRING "scanoutb;mult0_is_saturated;mult1_is_saturated;mult2_is_saturated;mult3_is_saturated" -- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1" -- Retrieval info: PRIVATE: SIGNB_REG STRING "0" -- Retrieval info: PRIVATE: WIDTHB STRING "8" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: OP1 STRING "Add" -- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "0" -- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: RNFORMAT STRING "16" -- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input" -- Retrieval info: PRIVATE: OP3 STRING "Add" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: INPUT_REGISTER_B2 STRING "UNREGISTERED" -- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "UNREGISTERED" -- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "UNUSED" -- Retrieval info: CONSTANT: INPUT_REGISTER_A2 STRING "UNREGISTERED" -- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "UNUSED" -- Retrieval info: CONSTANT: MULTIPLIER_REGISTER2 STRING "CLOCK0" -- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "3" -- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED" -- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "UNREGISTERED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add" -- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "UNUSED" -- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "UNREGISTERED" -- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "16" -- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB" -- Retrieval info: CONSTANT: MULTIPLIER_ACLR2 STRING "UNUSED" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "UNREGISTERED" -- Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB" -- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA" -- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO" -- Retrieval info: CONSTANT: INPUT_SOURCE_B2 STRING "DATAB" -- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA" -- Retrieval info: CONSTANT: INPUT_SOURCE_A2 STRING "DATAA" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "UNREGISTERED" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" -- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "UNREGISTERED" -- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "UNREGISTERED" -- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "UNUSED" -- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0" -- Retrieval info: USED_PORT: dataa_0 0 0 8 0 INPUT GND "dataa_0[7..0]" -- Retrieval info: USED_PORT: dataa_1 0 0 8 0 INPUT GND "dataa_1[7..0]" -- Retrieval info: USED_PORT: datab_0 0 0 8 0 INPUT GND "datab_0[7..0]" -- Retrieval info: USED_PORT: dataa_2 0 0 8 0 INPUT GND "dataa_2[7..0]" -- Retrieval info: USED_PORT: datab_1 0 0 8 0 INPUT GND "datab_1[7..0]" -- Retrieval info: USED_PORT: datab_2 0 0 8 0 INPUT GND "datab_2[7..0]" -- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT GND "result[15..0]" -- Retrieval info: CONNECT: @datab 0 0 8 8 datab_1 0 0 8 0 -- Retrieval info: CONNECT: @datab 0 0 8 16 datab_2 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0 -- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 -- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa_0 0 0 8 0 -- Retrieval info: CONNECT: @dataa 0 0 8 8 dataa_1 0 0 8 0 -- Retrieval info: CONNECT: @dataa 0 0 8 16 dataa_2 0 0 8 0 -- Retrieval info: CONNECT: @datab 0 0 8 0 datab_0 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL multiply3_8x8_add.vhd TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL multiply3_8x8_add.inc TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL multiply3_8x8_add.cmp TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL multiply3_8x8_add.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL multiply3_8x8_add_inst.vhd TRUE FALSE