-------------------------------------------------------------------------------
-- Title       : saa_rgb
-------------------------------------------------------------------------------
-- File        : saa_rgb.vhd
-- Author      : Frederic Lochon
-------------------------------------------------------------------------------
-- Description :
--
-- conversion du bus VPO du SAA vers un flux RGB selon les modes 16 ou 24 bits
--
-------------------------------------------------------------------------------
-- Modification history :
-- 2006/11/08 : created
-------------------------------------------------------------------------------

LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY saa_rgb IS
	PORT (
		r			: out std_logic_vector(7 downto 0);
		g			: out std_logic_vector(7 downto 0);
		b			: out std_logic_vector(7 downto 0);
		vpo			: in std_logic_vector(15 downto 0);
		llc2		: in std_logic;
		mode		: in std_logic
	);
END saa_rgb ;

ARCHITECTURE simple OF saa_rgb IS 

signal r_tmp			: std_logic_vector(7 downto 0);
signal g_tmp			: std_logic_vector(7 downto 0);
signal b_tmp			: std_logic_vector(7 downto 0);

BEGIN

	sampling : process(mode,llc2, vpo)
	begin
		if mode = '0' then
			r_tmp(7 downto 3) <= vpo(15 downto 11);
			g_tmp(7 downto 2) <= vpo(10 downto 5);
			b_tmp(7 downto 3) <= vpo(4 downto 0);

			r_tmp(2 downto 0) <= "000";
			g_tmp(1 downto 0) <= "00";
			b_tmp(2 downto 0) <= "000";
		elsif rising_edge(llc2) then
			r_tmp(7 downto 3) <= vpo(15 downto 11);
			g_tmp(7 downto 5) <= vpo(10 downto 8);
			r_tmp(2 downto 0) <= vpo(7 downto 5);
			g_tmp(1 downto 0) <= vpo(4 downto 3);
			b_tmp(2 downto 0) <= vpo(2 downto 0);
		elsif falling_edge(llc2) then
			g_tmp(4 downto 2) <= vpo(7 downto 5);
			b_tmp(7 downto 3) <= vpo(4 downto 0);
		end if;
	end process;

	registering : process(llc2)
	begin
		if rising_edge(llc2) then
			r <= r_tmp;
			g <= g_tmp;
			b <= b_tmp;
		end if;
	end process;
	
end simple;