------------------------------------------------------------------------------
-- Carte :		Cam-ass-ultra
-- Fonction : 	SAA signals decoder
-- Author :		crazyfred EIRBOT 2006
-- Date :		01.05.2006
------------------------------------------------------------------------------

library IEEE, work;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 
use work.all;

entity saa_tb is
	port (
		s_line_num  : out std_logic_vector(8 downto 0);
		s_pixel_num : out std_logic_vector(9 downto 0);

		s_blank     : out std_logic;
		s_sync      : out std_logic;
		s_image     : out std_logic
	);

end saa_tb;


architecture structure of saa_tb is

component saa_decode is
	port (
		LLC2      : in std_logic;
		RESETn    : in std_logic;

		HS        : in std_logic;	-- SAA: synchro trame
		VS        : in std_logic;	-- SAA: synchro ligne
		HREF      : in std_logic;	-- SAA: pixels actifs
		VREF      : in std_logic;

		line_num  : out std_logic_vector(8 downto 0);
		pixel_num : out std_logic_vector(9 downto 0);

		RTS0      : in std_logic;
		
		blank     : out std_logic;
		sync      : out std_logic;
		image     : out std_logic

	);
	end component;

	signal sLLC2 : std_logic;
	signal sRESETn : std_logic;
	signal sHS : std_logic;
	signal sVS : std_logic;
	signal sVREF : std_logic;
	signal sHREF : std_logic;
	signal sRTS0 : std_logic;
	
--	signal s_line_num : std_logic_vector(8 downto 0);
--	signal s_pixel_num : std_logic_vector(9 downto 0);
--	signal s_blank : std_logic;
--	signal s_sync : std_logic;
--	signal s_image : std_logic;
	
	begin

test : saa_decode 
	PORT MAP
	(
		LLC2 => sLLC2,
		RESETn => sRESETn,
		HS => sHS,
		VS => sVS,
		HREF => sHREF,
		VREF => sVREF,
		line_num => s_line_num,
		pixel_num => s_pixel_num,
		RTS0 => sRTS0,
		blank => s_blank,
		sync => s_sync,
		image => s_image
	);

-------------------------------------------------------------------------------
	
	horloge : process
	begin
		sLLC2 <= '0', '1' after 0.5 us;
		wait for 1 us;
	end process;

-------------------------------------------------------------------------------

	sRESETn <= '1';

-------------------------------------------------------------------------------

	sHS <= '0';

-------------------------------------------------------------------------------

	sVS <= '1';

-------------------------------------------------------------------------------

	horiz : process
	begin
		sHREF <= '0', '1' after 144 us;
		wait for 864 us;
	end process;

-------------------------------------------------------------------------------

	verti : process
	begin
		sVREF <= '0', '1' after 11232 us;
		wait for 112320 us;
	end process;

-------------------------------------------------------------------------------

	field : process
	begin
		sRTS0 <= '0', '1' after 112320 us;
		wait for 224640 us;
	end process;

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

	end structure;