------------------------------------------------------------------------------
-- Carte :		Cam-ass-ultra
-- Fonction : 	Simple sharer
-- Author :		crazyfred / EIRBOT 2006
-- Date :		19.05.2006
------------------------------------------------------------------------------

library IEEE, work;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 
use work.all;

entity simple_sharer is
	port (
		request_atmel : in std_logic;
		granted_atmel : out std_logic;
		rdaddress_sig : in std_logic_vector(7 downto 0);

		end_of_frame : in std_logic;
		choix : out std_logic_vector(7 downto 0);
		cpt_row : in std_logic_vector(9 downto 0);

		data_in : in std_logic_vector(11 downto 0);
		data_out : out std_logic_vector(11 downto 0);

		clk : in std_logic;
		statusfifo : out std_logic_vector(7 downto 0)
	);

end simple_sharer;


architecture structure of simple_sharer is

	signal fifo_status : std_logic_vector(1 downto 0);
	signal palet_status : std_logic_vector(1 downto 0);
	signal request_palet : std_logic;
	signal granted_palet : std_logic;

	signal enable_wr, enable_rd : std_logic;
	signal choix_sig : std_logic_vector(7 downto 0);
	signal data_sig, q_sig : std_logic_vector(15 downto 0);

component rampalets
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
end component;

begin

	data_sig(11 downto 0) <= data_in;
	data_sig(15 downto 12) <= "0000";
	data_out <= q_sig(11 downto 0);

	choix <= choix_sig;
	statusfifo <= choix_sig(2 downto 0)&end_of_frame&palet_status&fifo_status;

	state_machine : process(clk, request_atmel, request_palet)
	begin
		if rising_edge(clk) then
			if fifo_status = "00" and request_palet = '1' then -- nouvelles donnees a ecrire
				fifo_status <= "01";
			elsif fifo_status = "00" and request_atmel = '1' then -- envie de lire les donnees
				fifo_status <= "10";
			elsif fifo_status = "10" and request_atmel = '0' then -- l'atmel n'en a plus besoin
				fifo_status <= "00";
			elsif fifo_status = "01" and request_palet = '0' then -- fin de remplissage
				fifo_status <= "00";
			elsif fifo_status = "11" then -- cas a la con.
				fifo_status <= "00";
			end if;				
		end if;
	end process;
-------------------------------------------------------------------------------
	granted_atmel <= '1' when fifo_status = "10" else '0';
	granted_palet <= '1' when fifo_status = "01" else '0';
-------------------------------------------------------------------------------


	machine_palet : process(clk, end_of_frame, cpt_row)
	begin
		if end_of_frame = '0' then
			palet_status <= "00";
		elsif rising_edge(clk) then
			if palet_status = "00" and cpt_row < 20 then
				palet_status <= "01"; -- demande d'acces
			elsif palet_status = "01" and granted_palet = '1' then
				palet_status <= "10"; -- access granted
			elsif palet_status = "10" and choix_sig = "11111111" then
				palet_status <= "00"; -- fini de remplir
			elsif palet_status = "11" then
				palet_status <= "00"; -- cas a la con
			end if;
		end if;
	end process;
-------------------------------------------------------------------------------
	request_palet <= '0' when palet_status = "00" else '1';
	enable_wr <= '1' when palet_status = "10" else '0';
-------------------------------------------------------------------------------
	gene_choix : process(clk, palet_status)
	begin
		if palet_status /= "10" then
			choix_sig <= "00000000";
		elsif rising_edge(clk) then
			choix_sig <= choix_sig + 1;
		end if;
	end process;
-------------------------------------------------------------------------------
rampalets_inst : rampalets PORT MAP (
		data	 => data_sig,
		wren	 => enable_wr,
		wraddress	 => choix_sig,
		rdaddress	 => rdaddress_sig,
		clock	 => clk,
		q	 => q_sig
	);

end structure;