LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY une_ligne_3bits IS
	PORT (
		clock		: in	std_logic;
		
		wren		: in	std_logic;
		pixel_num	: in	std_logic_vector(9 downto 0);

		data_sig	: IN	STD_LOGIC_VECTOR(2 DOWNTO 0);
		
		q_n		: out	STD_LOGIC_VECTOR(2 DOWNTO 0); -- q(addr)
		q_n1	: out	STD_LOGIC_VECTOR(2 DOWNTO 0); -- q(addr-1)
		q_n2	: out	STD_LOGIC_VECTOR(2 DOWNTO 0); -- q(addr-2)
		q_n3	: out	STD_LOGIC_VECTOR(2 DOWNTO 0)  -- q(addr-3)
	);

END une_ligne_3bits ;

ARCHITECTURE a OF une_ligne_3bits IS

component ram_3bits
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
	);
end component;

signal q_A, q_B, q_C, q_D : std_logic_vector(2 downto 0);

BEGIN

	delay : process(clock)
	begin
		if rising_edge(clock) then
			q_B <= q_A;
			q_C <= q_B;
			q_D <= q_C;
		end if;
	end process;

	q_n <= q_A;
	q_n1 <= q_B;
	q_n2 <= q_C;
	q_n3 <= q_D;
	
	ram : ram_3bits PORT MAP (
		address	 => pixel_num,
		clock	 => clock,
		data	 => data_sig,
		wren	 => wren,
		q	 => q_A
	);

END a;