------------------------------------------------------------------------------
-- Affaire :   ROBOT
-- Carte :		Camera
-- EPLD :		Epld_
-- Fonction : 	Ball Finder v2 !
-- Author :		EIRBOT 2003 ENSEIRB
-- Date :		25.10.2002
------------------------------------------------------------------------------

library IEEE, work;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 
use work.all;

entity atmel is
	port (
		A     : in std_logic_vector(15 downto 8);
		AD     : inout std_logic_vector(7 downto 0);

		ALE  : in std_logic;
		ReadN  : in std_logic;
		WriteN : in std_logic;

		entree00000 : in std_logic_vector(7 downto 0);
		entree00001 : in std_logic_vector(7 downto 0);
		entree00010 : in std_logic_vector(7 downto 0);
		entree00011 : in std_logic_vector(7 downto 0);
		entree00100 : in std_logic_vector(7 downto 0);

		sortie00000 : out std_logic_vector(7 downto 0);
		sortie00001 : out std_logic_vector(7 downto 0);
		sortie00010 : out std_logic_vector(7 downto 0);
		sortie00011 : out std_logic_vector(7 downto 0);
		sortie00100 : out std_logic_vector(7 downto 0)

	);

end atmel;


architecture structure of atmel is

	signal Address : std_logic_vector(15 downto 0);
	signal Data_out : std_logic_vector(7 downto 0); -- sortie vers l'atmel
	signal Data_in : std_logic_vector(7 downto 0); -- entree dans le FPGA

	signal choix : std_logic_vector(4 downto 0);

	begin

	Address(15 downto 8) <= A(15 downto 8);

-------------------------------------------------------------------------------
	demux : process(ALE, ReadN, WriteN, AD, Data_out)
	begin
		if (ALE = '1') then
			Address(7 downto 0) <= AD(7 downto 0);
		elsif (ReadN = '0') then
			AD(7 downto 0) <= Data_out;
		elsif (WriteN = '0') then
			Data_in <= AD(7 downto 0);
		else
			AD <= "ZZZZZZZZ";
		end if;
	end process;
-------------------------------------------------------------------------------
	choix <= Address(4 downto 0);
-------------------------------------------------------------------------------
	lecture : process (choix, ReadN)
	begin
		if (ReadN = '0') then
			case choix is
				when "00000" => Data_out <= entree00000;
				when "00001" => Data_out <= entree00001;
				when "00010" => Data_out <= entree00010;
				when "00011" => Data_out <= entree00011;
				when "00100" => Data_out <= entree00100;
				when others => Data_out <= "00000000";
			end case;
		end if;
	end process;
-------------------------------------------------------------------------------
	ecriture : process (choix, WriteN)
	begin
		if (WriteN = '0') then
			case choix is
				when "00000" => sortie00000 <= Data_in;
				when "00001" => sortie00001 <= Data_in;
				when "00010" => sortie00010 <= Data_in;
				when "00011" => sortie00011 <= Data_in;
				when "00100" => sortie00100 <= Data_in;
				when others => NULL;
			end case;
		end if;
	end process;
-------------------------------------------------------------------------------
	end structure;