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-- Carte :		Cam-ass-ultra
-- Fonction : 	SAA signals decoder
-- Author :		crazyfred EIRBOT 2006
-- Date :		01.05.2006
------------------------------------------------------------------------------

library IEEE, work;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 
use work.all;

entity recorder is
	port (
		LLC2      : in std_logic;

		start_recording : in std_logic;

		ram_granted : in std_logic;

		pixel     : in std_logic_vector(15 downto 0);
		line_num  : in std_logic_vector(8 downto 0);
		pixel_num : in std_logic_vector(9 downto 0);
		
		whichram : in std_logic;
		
		request : out std_logic;
		request_type : out std_logic_vector(1 downto 0);
		recording : out std_logic_vector(7 downto 0);
		Data : inout std_logic_vector(15 downto 0);
		WR_L : out std_logic;
		WR_H : out std_logic;
		Address   : out std_logic_vector(18 downto 0)

	);

end recorder;


architecture structure of recorder is

	signal recordstate : std_logic_vector(1 downto 0);

	begin

	request_type <= '0'&whichram; -- ramV ou ramT

	recording(1 downto 0) <= recordstate;
	recording(4 downto 2) <= line_num(2 downto 0);
	recording(7 downto 5) <= pixel_num(2 downto 0);

	statemachine : process(LLC2, start_recording, ram_granted)
	begin
		if rising_edge(LLC2) then
			if start_recording = '1' and recordstate = "00" then
				recordstate <= "01"; -- demande d'acces
			elsif recordstate = "01" and ram_granted = '1' and line_num = "000000001" and pixel_num = "0000000000" then
				recordstate <= "10"; -- acces autorise et debut de trame, on peut enregistrer
			elsif recordstate = "10" and line_num = "011010010" then
				recordstate <= "00"; -- fin de trame, c'est fini.
			elsif recordstate = "11" then
				recordstate <= "00"; -- etat a la con, on reset.
			end if;
		end if;
	end process;

	ram_request : process (recordstate)
	begin
		-- demande/maintient d'acces a la ram si on veut RECORD ou si on est entrain de RECORD
		if recordstate = "01" or recordstate = "10" then
			request <= '1';
		else
			request <= '0';
		end if;
	end process;

	sampling : process(LLC2, line_num, pixel_num, pixel, recordstate)
	begin
		if recordstate /= "10" then
			Address <= "0000000000000000000";
			Data <= "ZZZZZZZZZZZZZZZZ";
		elsif rising_edge(LLC2) then
			Address <= line_num & pixel_num;
			Data <= pixel;
		end if;
	end process;

	ram_access : process(recordstate, LLC2)
	begin
		if recordstate = "10" then -- on enregistre
			WR_L <= LLC2;
			WR_H <= LLC2;
		else
			WR_L <= '1';
			WR_H <= '1';
		end if;
	end process;

-------------------------------------------------------------------------------
	end structure;