------------------------------------------------------------------------------- -- Title : filtre pixel -- Project : ------------------------------------------------------------------------------- -- File : filtre.vhd -- Author : Frederic Lochon -- Company : -- Last update : 2002/12/10 -- Platform : ------------------------------------------------------------------------------- -- Description : -- filtre de pixels parasites regardant la predomiance de couleur ------------------------------------------------------------------------------- -- Modification history : -- 2002/11/29 : created ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity filtre is generic ( window_down : integer range 0 to 511 := 400; window_up : integer range 0 to 511 := 100; window_right : integer range 0 to 1023 := 800; window_left : integer range 0 to 1023 := 200; precision_filtre : integer := 5; largeur_seuil : integer := 2); port ( cpt_line : IN integer range 0 to 511; cpt_row : IN integer range 0 to 1023; cpt_row_out : OUT integer range 0 to 1023; cpt_line_out : OUT integer range 0 to 511; red_out : OUT std_logic; gre_out : OUT std_logic; blu_out : OUT std_logic; red_in : IN std_logic; gre_in : IN std_logic; blu_in : IN std_logic; so_win : OUT std_logic; reset_n : IN std_logic; clock : IN std_logic ); end filtre; architecture dominant of filtre is signal row_vector : std_logic_vector(9 downto 0); signal line_vector : std_logic_vector(8 downto 0); signal red_pipe, gre_pipe, blu_pipe : std_logic_vector(precision_filtre - 1 downto 0); signal cpt_red, cpt_gre : integer range 0 to precision_filtre ; signal en_win : std_logic; signal write_ram0,write_ram1 : std_logic; signal write_ram2,write_ram3 : std_logic; signal write_ram4,write_ram5 : std_logic; signal write_ram6,write_ram7 : std_logic; signal red_pixel, gre_pixel, blu_pixel : std_logic; signal en_ram : std_logic; signal din, dout0, dout1, dout2, dout3 : std_logic_vector(2 downto 0); signal dout, dout4, dout5, dout6, dout7 : std_logic_vector(2 downto 0); signal d_0, d_1, d_2, d_3, d_4, d_5, d_6: std_logic_vector(2 downto 0); component ram_10x4 port ( addr : IN std_logic_VECTOR(9 downto 0); clk : IN std_logic; din : IN std_logic_VECTOR(2 downto 0); dout : OUT std_logic_VECTOR(2 downto 0); en : IN std_logic; we : IN std_logic); end component; begin -- dominant RAM0 : ram_10x4 port map ( addr => row_vector(9 downto 0), clk => clock, din => din, dout => dout0, en => en_ram, we => write_ram0); RAM1 : ram_10x4 port map ( addr => row_vector(9 downto 0), clk => clock, din => din, dout => dout1, en => en_ram, we => write_ram1); RAM2 : ram_10x4 port map ( addr => row_vector(9 downto 0), clk => clock, din => din, dout => dout2, en => en_ram, we => write_ram2); RAM3 : ram_10x4 port map ( addr => row_vector(9 downto 0), clk => clock, din => din, dout => dout3, en => en_ram, we => write_ram3); ------------------------------------------------------------------------------- -- -- |-----| -- |ram 0| -- |-----| |-------------| -- |----| | | -- |DMUX| | | -- |----| | | -- |-----| | | -- |ram 1| | | -- |-----| | | -- |---| |----| | | -- |MUX| |DMUX| | filtrage | -- |---| |----| | | -- |-----| | | -- |ram 2| | | -- |-----| | | -- |----| | | -- |DMUX| | | -- |----| | | -- |-----| |-------------| -- |ram 3| -- |-----| -- ------------------------------------------------------------------------------- row_vector <= std_logic_vector(to_unsigned(cpt_row, 10)); line_vector <= std_logic_vector(to_unsigned(cpt_line, 9)); write_ram0 <= not line_vector(0) and not line_vector(1); -- 0 write_ram1 <= line_vector(0) and not line_vector(1); -- 1 write_ram2 <= not line_vector(0) and line_vector(1); -- 2 write_ram3 <= line_vector(0) and line_vector(1); -- 3 din(2) <= red_pixel; din(1) <= gre_pixel; din(0) <= blu_pixel; en_ram <= '1'; with line_vector(1 downto 0) select d_0 <= dout3(2 downto 0) when "00", dout0(2 downto 0) when "01", dout1(2 downto 0) when "10", dout2(2 downto 0) when others; with line_vector(1 downto 0) select d_1 <= dout2(2 downto 0) when "00", dout3(2 downto 0) when "01", dout0(2 downto 0) when "10", dout1(2 downto 0) when others; with line_vector(1 downto 0) select d_2 <= dout1(2 downto 0) when "00", dout2(2 downto 0) when "01", dout3(2 downto 0) when "10", dout0(2 downto 0) when others; dout <= d_0 when (d_0 = d_1) else d_1 when (d_1 = d_2) else d_2 when (d_0 = d_2) else "000"; -- prout : process (d_0, d_1, d_2) -- begin -- if d_0 = d_1 and d_1 = d_2 then -- dout <= d_0; -- else -- dout <= "111"; -- end if; -- end process; red_out <= dout(2); gre_out <= dout(1); blu_out <= dout(0); ------------------------------------------------------------------------------- so_win <= en_win; ------------------------------------------------------------------------------- filtre_pixel: process (clock, reset_n, cpt_row) -- filtre du bruit sur une ligne begin if (reset_n='0') or (cpt_row=0) then red_pixel <= '0'; gre_pixel <= '0'; blu_pixel <= '0'; cpt_row_out <= 0; cpt_line_out <= 0; en_win <= '0'; red_pipe <= std_logic_vector(to_unsigned(0,precision_filtre)); gre_pipe <= std_logic_vector(to_unsigned(0,precision_filtre)); blu_pipe <= std_logic_vector(to_unsigned(0,precision_filtre)); cpt_red <= 0; cpt_gre <= 0; elsif (rising_edge(clock)) then -- on se prepare a decaler -- on decompte le pixel qui va sortir -- on regarde le nouveau pixel et on le compte if (red_pipe(precision_filtre-1)='1' and gre_pipe(precision_filtre-1)='0' and blu_pipe(precision_filtre-1)='0') then if not (red_in='1' and gre_in='0' and blu_in='0') then cpt_red <= cpt_red - 1; end if; elsif red_in='1' and gre_in='0' and blu_in='0' then if not (red_pipe(precision_filtre-1)='1' and gre_pipe(precision_filtre-1)='0' and blu_pipe(precision_filtre-1)='0') then cpt_red <= cpt_red + 1; end if; end if; if (red_pipe(precision_filtre-1)='0' and gre_pipe(precision_filtre-1)='1' and blu_pipe(precision_filtre-1)='0') then if not (red_in='0' and gre_in='1' and blu_in='0') then cpt_gre <= cpt_gre - 1; end if; elsif red_in='0' and gre_in='1' and blu_in='0' then if not (red_pipe(precision_filtre-1)='0' and gre_pipe(precision_filtre-1)='1' and blu_pipe(precision_filtre-1)='0')then cpt_gre <= cpt_gre + 1; end if; end if; -- on decale -- on fait entrer un nouveau pixel red_pipe <= red_pipe(precision_filtre-2 downto 0) & red_in; gre_pipe <= gre_pipe(precision_filtre-2 downto 0) & gre_in; blu_pipe <= blu_pipe(precision_filtre-2 downto 0) & blu_in; -- on regarde la dominance de la couleur: -- la couleur dominante subit un trigger de schmidt if cpt_red > cpt_gre then if cpt_red > precision_filtre/2 + largeur_seuil/2 then red_pixel <= '1'; gre_pixel <= '0'; blu_pixel <= '0'; elsif cpt_red < precision_filtre/2 - largeur_seuil/2 then red_pixel <= '1'; gre_pixel <= '1'; blu_pixel <= '1'; end if; else if cpt_gre > precision_filtre/2 + largeur_seuil/2 then red_pixel <= '0'; gre_pixel <= '1'; blu_pixel <= '0'; elsif cpt_gre < precision_filtre/2 - largeur_seuil/2 then red_pixel <= '1'; gre_pixel <= '1'; blu_pixel <= '1'; end if; end if; cpt_row_out <= cpt_row; cpt_line_out <= cpt_line; -- fenetrage if ((cpt_line < window_down) and (cpt_line > window_up) and (cpt_row < window_right) and (cpt_row > window_left)) then en_win <= '1'; else en_win <= '0'; end if; end if; end process; end dominant;