LIBRARY IEEE, work; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; use work.all; ENTITY testbench IS PORT( b_VREF_XIL : out std_logic; b_LLC2_XIL : out std_logic; b_HREF_XIL : out std_logic; b_d_out : out std_logic_vector(11 downto 0); b_INT4 : out std_logic; b_INT5 : out std_logic; b_INT6 : out std_logic; b_INT7 : out std_logic ); END testbench; ARCHITECTURE struct OF testbench IS signal b_CLK : std_logic; signal b_RESETn : std_logic; -- Reset actif a 0 signal b_HS : std_logic; -- Venant SAA -> synchro trame signal b_VS : std_logic; -- Venant SAA -> synchro ligne signal b_HREF : std_logic; -- Pixels actifs signal b_VREF : std_logic; signal b_BYPASS : std_logic; signal b_entree : std_logic_vector(7 DOWNTO 0); signal w_CLK : std_logic; signal r_CLK : std_logic; signal b_OUT_RED : std_logic; signal b_OUT_GRE : std_logic; signal b_OUT_BLU : std_logic; signal l_rouge : unsigned( 7 DOWNTO 0 ); signal l_vert : unsigned( 7 DOWNTO 0 ); signal l_bleu : unsigned( 7 DOWNTO 0 ); signal w_rouge : unsigned( 7 DOWNTO 0 ); signal w_vert : unsigned( 7 DOWNTO 0 ); signal w_bleu : unsigned( 7 DOWNTO 0 ); constant llc : time := 37 ns; constant ligne : time := 1728*llc; -- 144 + 720 llc2 signal cpt_lignes : integer; component ballfind port ( LLC2 : in std_logic; RESETn : in std_logic; BYPASS : in std_logic; HS : in std_logic; VS : in std_logic; HREF : in std_logic; VREF : in std_logic; EPROM : in std_logic_vector(7 downto 0); OUT_RED : out std_logic; OUT_BLU : out std_logic; OUT_GRE : out std_logic; VREF_XIL : out std_logic; LLC2_XIL : out std_logic; HREF_XIL : out std_logic; d_out : out std_logic_vector(11 downto 0); INT4 : out std_logic; INT5 : out std_logic; INT6 : out std_logic; INT7 : out std_logic ); end component; for XILINX1 : ballfind use entity work.ballfind(structure); component ecriture GENERIC ( nom_fichier : string; en_tete : string; largeur : natural; hauteur : natural; couleur_max : natural ); PORT ( rouge : IN unsigned( 7 DOWNTO 0 ) ; vert : IN unsigned( 7 DOWNTO 0 ) ; bleu : IN unsigned( 7 DOWNTO 0 ) ; h : IN std_logic ); end component; component lecture GENERIC ( nom_fichier : string; en_tete : string; largeur : natural; hauteur : natural; couleur_max : natural ); PORT ( rouge : OUT unsigned(7 DOWNTO 0); vert : OUT unsigned(7 DOWNTO 0); bleu : OUT unsigned(7 DOWNTO 0); h : IN std_logic ); end component; for LECTURE1 : lecture use entity work.lecture(sans_tableau); for ECRITURE1 : ecriture use entity work.ecriture(ecriture); BEGIN XILINX1 : ballfind port map ( LLC2 => b_CLK, RESETn => b_RESETn, HS => b_HS, VS => b_VS, HREF => b_HREF, VREF => b_VREF, EPROM => b_entree, BYPASS => b_BYPASS, OUT_RED => b_OUT_RED, OUT_BLU => b_OUT_BLU, OUT_GRE => b_OUT_GRE, VREF_XIL => b_VREF_XIL, LLC2_XIL => b_LLC2_XIL, HREF_XIL => b_HREF_XIL, d_out => b_d_out, INT4 => b_INT4, INT5 => b_INT5, INT6 => b_INT6, INT7 => b_INT7 ); LECTURE1 : lecture generic map ( nom_fichier => "005.ppm", en_tete => "P3", largeur => 720, hauteur => 288, couleur_max => 255) port map ( rouge => l_rouge, vert => l_vert, bleu => l_bleu, h => r_CLK); ECRITURE1 : ecriture generic map ( nom_fichier => "005_processed_lignes.ppm", en_tete => "P3", largeur => 720, hauteur => 288, couleur_max => 255) port map ( rouge => w_rouge, vert => w_vert, bleu => w_bleu, h => w_CLK); ------------------------------------------------------------------------------- re_rouge: process (l_rouge) begin -- process if l_rouge > 127 then b_entree(0) <= '1'; else b_entree(0) <= '0'; end if; end process; ------------------------------------------------------------------------------- re_vert: process (l_vert) begin -- process if l_vert > 127 then b_entree(1) <= '1'; else b_entree(1) <= '0'; end if; end process; ------------------------------------------------------------------------------- re_bleu: process (l_bleu) begin -- process if l_bleu > 127 then b_entree(2) <= '1'; else b_entree(2) <= '0'; end if; end process; ------------------------------------------------------------------------------- wr_rouge: process (b_OUT_RED) begin if b_OUT_RED = '1' then w_rouge <= to_unsigned(255,8); else w_rouge <= to_unsigned(0,8); end if; end process; ------------------------------------------------------------------------------- wr_vert: process (b_OUT_GRE) begin if b_OUT_GRE = '1' then w_vert <= to_unsigned(255,8); else w_vert <= to_unsigned(0,8); end if; end process; ------------------------------------------------------------------------------- wr_bleu: process (b_OUT_BLU) begin if b_OUT_BLU = '1' then w_bleu <= to_unsigned(255,8); else w_bleu <= to_unsigned(0,8); end if; end process; ------------------------------------------------------------------------------- horloge: process begin b_CLK <= '0', '1' after llc; wait for 2*llc; end process; ------------------------------------------------------------------------------- reset: process begin b_RESETn <= '0', '1' after 10 ns; wait for 100 ms; end process; ------------------------------------------------------------------------------- h_ref: process begin b_HREF <= '0', '1' after 144*2*llc; wait for ligne; end process; ------------------------------------------------------------------------------- h_s: process begin b_HS <= '1', '0' after 43*2*llc, '1' after (144+720-27)*2*llc; wait for ligne; end process; ------------------------------------------------------------------------------- comptage_lignes: process(b_RESETn, b_HREF) begin if (b_RESETn = '0') then cpt_lignes <= 0; elsif falling_edge(b_HREF) then cpt_lignes <= cpt_lignes+1; end if; end process; ------------------------------------------------------------------------------- v_ref: process(b_HREF) begin if ( (cpt_lignes> 22) and (cpt_lignes<311) ) or ( (cpt_lignes>335) and (cpt_lignes<624) ) then b_VREF <= '1'; else b_VREF <= '0'; end if; end process; ------------------------------------------------------------------------------- b_VS <= '0'; r_CLK <= b_CLK AND b_HREF AND b_VREF; w_CLK <= b_CLK AND b_HREF AND b_VREF; b_BYPASS <= '1'; b_entree(7) <= '0'; b_entree(6) <= '0'; b_entree(5) <= '0'; b_entree(4) <= '0'; b_entree(3) <= '0'; ------------------------------------------------------------------------------- END struct;