LIBRARY IEEE, work;
USE IEEE.STD_LOGIC_1164.ALL;
use work.all;

ENTITY carte_xc2s150 IS
  PORT( 
    b_CLK	: in  std_logic; 	-- Horloge 27MHZ egale a LLC
    b_RESETn	: in  std_logic; 	-- Reset actif a 0

    b_HS	: in  std_logic;	        -- Venant SAA -> synchro trame
    b_VS	: in  std_logic;	        -- Venant SAA -> synchro ligne
    b_HREF      : in  std_logic;         -- Pixels actifs
    b_VREF	: in  std_logic;

    b_BYPASS	: in  std_logic;
    
	 b_STROBE   : in  std_logic;

    b_OUT_RED	: out std_logic;
    b_OUT_BLU	: out std_logic;
    b_OUT_GRE	: out std_logic;

    b_VREF_XIL	: out std_logic;
    b_HREF_XIL	: out std_logic;
    b_LLC2_XIL	: out std_logic;

    b_INT4	: out std_logic;
    b_INT5      : out std_logic;
    b_INT6      : out std_logic;
    b_INT7      : out std_logic;

    b_d_out     : out std_logic_vector(11 downto 0);

    b_entree    : in  std_logic_vector(7 DOWNTO 0)

    );
   
END  carte_xc2s150;




ARCHITECTURE struct OF carte_xc2s150 IS
  
  component ballfind
    port (
      LLC2	   : in  std_logic;
      RESETn	: in  std_logic;

      BYPASS	: in  std_logic;

		STROBE   : in  std_logic;
      HS	      : in  std_logic;
      VS	      : in  std_logic;
      HREF     : in  std_logic;
      VREF	   : in  std_logic;

      EPROM    : in  std_logic_vector(7 downto 0);

      OUT_RED	: out std_logic;
      OUT_BLU	: out std_logic;
      OUT_GRE	: out std_logic;

      VREF_XIL	: out std_logic;
      LLC2_XIL	: out std_logic;
      HREF_XIL	: out std_logic;

      d_out    : out std_logic_vector(11 downto 0);

      INT4     : out std_logic;
      INT5	   : out std_logic;
      INT6	   : out std_logic;
      INT7	   : out std_logic
      );
  end component;
  
  for XILINX1 : ballfind
    use entity work.ballfind(structure);
  
BEGIN
  
  XILINX1 : ballfind
    port map (

      LLC2	=> b_CLK,
      RESETn	=> b_RESETn,

		STROBE => b_STROBE,

      HS	=> b_HS,
      VS	=> b_VS,
      HREF      => b_HREF,
      VREF	=> b_VREF,

      EPROM	=> b_entree,

      BYPASS	=> b_BYPASS,

      OUT_RED	=> b_OUT_RED,
      OUT_BLU	=> b_OUT_BLU,
      OUT_GRE	=> b_OUT_GRE,

      VREF_XIL	=> b_VREF_XIL,
      LLC2_XIL	=> b_LLC2_XIL,
      HREF_XIL	=> b_HREF_XIL,

      d_out     => b_d_out,

      INT4	=> b_INT4,
      INT5	=> b_INT5,
      INT6	=> b_INT6,
      INT7	=> b_INT7
      );
  
END struct;